Project Characterization

1. Project Characterization 16.11.2010 Implementing a compressor in software and decompression in hardware Presents by - Schreiber Beeri YavichAlon • Guided by – Porian Moshe

2. Intro Gym Control Room Gym Compressed data (Wireless) ❤ ❤ 142 132 ❤ ❤ 170 79 ❤ ❤ 130 127

3. Intro (Cont.) Problem • Data transmission time • Processing time • Complex layout

4. Intro (Cont.) Solution • Transmitter Compresses the data • Receiver extracts and displays the data

5. Project’s goal • Implement a software compressor with a hardware extractor. • Compressor -> Matlab • Extractor -> FPGA

6. Algorithm • Run Length • Transmit Value & Repetitions

7. Algorithm -simple Example • Picture pixel’s Values: • Transmitted data : 0 0 0 0 0 0 255 255 255 120

8. Project’s requirements • Input of 640*480 picture resolution. • Programming “Run length algorithm” in Matlab, using it as the compressor. • Creating a data array from the algorithm’s output and wrapping it in a pre determined packet. • Sending the packet to the FPGA through serial communication using RS-232 protocol.

9. Project’s requirements (Cont.) • Checking the compressed data in the FPGA for errors with a pre determined CRC. • Storing the compressed data to an external memory - SDRAM • Implementation of the extractor within the FPGA using VHDL. • Presenting the extracted data on display with VESA protocol.

10. Project’s requirements Displayed Picture (800x600) Picture to be compressed (640x480) DE2 Board HOST VGA

11. Message Pack Structure 8 bits SOF 1 Byte Type 1 Byte Address 3 Bytes Data Length 1 Bytes Data (Payload) Up to 1 Kbytes (2 SDRAM’s full page) CRC 1 Bytes EOF 1 Bytes

12. TOP architecture

13. FPGA – Cyclone II REGISTERS Packet TX Host Matlab RAM MUX Message Encoder UART TXP TX 115,200KBit/sec RX Packet RX UART RXP RAM DEC Message Decoder Sys. Clk PLL Ext. Clk Mem Write CRC Reset D’ bouncer Sys. Rst Ext. Reset Mem Read Arbiter VGA Display Display Controller SDRAM Controller RunLen Decoder IS42S16400 SDRAM VESA 800x600

14. Matlab GUI (debug version) Compression Time Compression Ratio

15. Compressed Data Example Compressed: Decompressed:

16. Micro architecture

17. VGA Display Matlab ISEOF FROM MSG_DEC VALID Line legend RESET TO CMP MSG_OK 1 bit VALID REQ Message Decoder RAM Controller 8 bits RD_adress 10 bits 16 bits Byte_in_pack n_pix RGB 22 bits Display Controller WR_addr WREN DATA Num Pixels 40MHz RAM UART UART RXD UART RXP REG Controller DATA EN DATA DATA FIFO (dual clock) VALID UART TXD from UART TX REQ DEC CRC CLC REG CRC RX REG TYPE REG Addr REG Len REG Type COL_EN COLOR ISEOF FROM MSG_DEC RunLen Decoder DATA DATA REGISTERS MP REGS CMP REG CRC STATUS RX_RDY to MEM READ DATA DATA_RDY from MEM READ REQ RESET FROM MSG_DEC Mem Write EN REP RX_RDY from MEM READ DATA_RDY to MEM READ Addr SDARM ACK DATA REQ SDRAM Controller COLOR DATA Arbiter Mem Read Data & Control Data & Control UART TXD to UART TX REQ VALID ACK TX PACK UART TXP DATA 40MHZ (VESA) Adress Reset Debouncer PLL Resets 50MHZ 133MHZ (SDRAM, System – optional ) REQ 80MHz (System - optional) VALID

18. Schedule

19. Schedule