Encryption Development System Project Part A Characterization

1. Encryption Development SystemProject Part A Characterization Written by: Yaakov Levenzon Ido Kahan Advisor: Mony Orbach Spring Semester 2012

2. The Problem We carry sensitive information with us, to practically everywhere… Where is it?!

3. Our Solution • The cyclone II FPGA is fast and quite strong, thus making the Encryption/Decryption process fast, and usable for different needs . • Easy to use: the entire process is invisible for the customer, which makes it easy and intuitive to use , just as using a regular disk-on-key (without the difficulty of technical details and the lack of skill). • The level of encryption is strong and changeable.The method of block cipher AES (Advanced Encryption Standard)is, De Facto, used by the U.S Government and the private sector.

4. Project Goals • Primary Goal: • Creating a complete system which encrypts and deciphers files and transfers them to a disk-on-key, by Implementing a symmetric blockcipher/decipher module on DE2 Board. • Didactic Goals: • Understanding and developing ways of communication between the PC and the DE2 board and its internal memory. • Understanding and implementing the Nios ІІ embedded processor, and transfer data by utilizing the Avalon bus.

5. The DE2 Board

6. Working Environment • Design, synthesis and P&R – Quartus • Simulation – Modelsim • Debugging – Modelsim • Debugging on the chip – SignalTap

7. Architecture DE2 FPGA Host AES DMA Nios II AES PC animation AVALON Disc on key USB CTRL Unencrypted Memory USB CTRL USB PHY & MAC Encrypted Memory USB PHY & MAC USB

8. Block Diagram - Writing FPGA Cable USB PC FPGA Memory Sending words Words by USB protocol Words on AVALON bus Unencrypted words PC Nios Nios Nios FPGA Memory AES Block Nios Encrypting words Encrypted words

9. Block Diagram - Reading FPGA Cable USB PC FPGA Memory Sending request Request by USB protocol Request on AVALON bus Reading encrypted words PC Nios Nios Cable USB Nios FPGA Memory AES Block Words by USB protocol Nios Nios PC Unencrypted words Decrypting

10. Nios II animation • Nios II/s Core – the best of two worlds • Can access up to 2 GB of external address space • Has instruction cache but no data cache • Has Brunch Prediction • Five stage pipeline

11. USB host and device CTRL

12. Avalon Bus Several signals: Clk Read Write Data : 1-32 We will use: 32 (g) Address: 1-32 We will use: 14 (g) animation

13. Planning ahead… • The first part is only a preparation for the AES system • Generic design • Improving the current system (Example: unused address lines) • Using (or creating?) a small File System for writing and reading filesfrom external memories, for example: Flash memory (disk-on-key), SD-card etc. • Final product: a complete system which can solve the problem • Opening (and selling…) a start up! 

14. Project Timetable

15. Thank you for listening

16. Enigma: Encryption & Decryption SystemProject Part B Characterization Written by: Yaakov Levenzon Ido Kahan Advisor: Mony Orbach Winter Semester 2013

17. The Problem We carry sensitive information with us, to practically everywhere… Where is it?!

18. What has we done so far? • FPGA Encryption/Decryption Verification SystemTop Level: Nios Encrypt_sys Fifo_out FSM Fifo_in controller

19. Problems with previous encryptions systems • AES - Same bank of Keys every time • AES – Use of limited FPGA resources • Repeated patterns makes it easy to decipher

20. Our Solution • The original Enigma machine: • In our systems: • More characters • More combinations • Start position to the ASCII table. • Every day -> different key.

21. Project Goals • Primary Goal: • Creating a complete system which encrypts and deciphers files by using the method of the famous “Enigma” machine, while following the instructions of our part A system.Didactic Goals: • Dealing with a design and implementation of a complete encryption/decryption system, thus strengthening our VHDL skills. • Implementing the Enigma system into our architecture (while using its generic ability to modify it for working with streams of data).

22. Our System’s Data Sheet • Maximum possible Encryption/Decryption memory size: 221696 bits (46% of DE2 board) • (Recommended size – for 85% capacity: 149120 bits) • Maximum possible Encryption/Decryption number of LE: 32645 • Key Size: 128 bits (Generic Design) • Data width: 128 bits (Generic Design) • System speed: 1 MBPS (dictated by the DLP module) • DLP FIFO size: 1024 bits • DLP FIFO Speed: 384 byte Transmit buffer / 128 byte receive buffer

23. Working Environment • Design, synthesis and P&R – Quartus • Simulation – Modelsim • Debugging – Modelsim • Debugging on the chip – SignalTap

24. Architecture – High Level DE2 FPGA controller Nios II Host PC DLP AVALON USB ENIGMA System Encryption/Decryption Out_Data FIFO 128->8 In_Data FIFO 8->128

25. The Algorithm – step 1 First rotor 0x01 0x02 0x03 0x04 0xFF 0xA2 0x4B 0x67 0x89 0xAC PC 0x02, 0x02 0x4B, 0xA2 1 ASCII table First key

26. Encryption Data Flow – step 2 First rotor Second rotor Third rotor 0x01 0x02 0x03 0x04 0xFF 0x01 0x02 0x03 0x04 0xFF 0xA2 0x4B 0x67 0x89 0xAC 0x14 0x98 0x76 0x94 0xE1 0x01 0x02 0x03 0x04 0xFF 0x23 0x55 0x09 0x11 0x2B Encrypted data 0x02, 0x02 Ox4B, OxA2 PC PC 1 1/2 1/3 ASCII table Key A ASCII table Key B Key C ASCII table

27. Keys – step 3 256*3=768 0x85........0x23 0x680x540x430xA20x28 0x13........0x38 0x740x780x040x120x43 0xEC........0x1A 0x3C0xA80xD50x550xF2 0x9F........0x3B 0x230xD20x890x170x98 31 PC RAM • Every rotor receives different key • The keys will be changed every day • The keys file will be saved in a safe file ASCII ASCII ASCII KEY A KEY B KEY C Second rotor Third rotor First rotor

28. The First Position – step 4 • Another level of security • Every rotor have a different first-position • The first-positions will be changed every day a rotor a rotor 0x01 0x02 0x03 0x04 0xFF 0xFE 0xFF 0x01 0x02 0xFD Promote 2 steps ASCII table ASCII table

29. First Positions For The Rotors – step 5 3 5 8 34 46 89 12 54 23 83 76 55 31 PC RAM • Another level of security • Every rotor have a different first-position • The first-positions will be changed every day • Two separated files: keys and positions ASCII ASCII ASCII KEY A KEY B KEY C Second rotor Third rotor First rotor

30. Decryption Algorithm • The encryption-system is symmetrical as the Enigma machine. • Should use the same keys, same positions for the keys and the same rotor-positions. First rotor 0x01 0x02 0x03 0x04 0xFF 0xA2 0x4B 0x67 0x89 0xAC ASCII table First key

31. Decryption Algorithm First rotor 0xA2 0x4B 0x67 0x89 0xAC 0x01 0x02 0x03 0x04 0xFF PC 0x4B, 0xA2 0x02, 0x02 Encrypted data 1 First key ASCII table

32. Decryption Data Flow Third rotor First rotor Second rotor 0x23 0x55 0x09 0x11 0x2B 0x14 0x98 0x76 0x94 0xE1 0x01 0x02 0x03 0x04 0xFF 0x01 0x02 0x03 0x04 0xFF 0x01 0x02 0x03 0x04 0xFF 0xA2 0x4B 0x67 0x89 0xAC Encrypted data 0x02, 0x02 Ox4B, OxA2 PC PC 1 1/2 1/3 Key C ASCII table Key B ASCII table Key A ASCII table

33. Another element of complexity • Using hopping method to determine how much the rotor will spin in every char encryption cycle.Both ends of the communication will know the function ahead so there is no need to send data for this method (less use of FPGA memory resources). • The function we will use will be a generation of Fibonacci sequence, with randomly chosen start conditions (we will need 2 random integers, different ones for each rotor).

34. Top Level – part B RAM key GUI for the user Rotor A Rotor A Rotor A keys file positions file DLP date mux Send data file send text RAM First-position RX text

35. Project Timetable E X A M Until the middle-presentation in the next month – encryption data flow should be ready to synthesis. Validation system written in C by Golden Model.

36. Thank you for listening