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Final Project Review. Team Vibraid April 2014. Vibraid. Michael Balanov (Mike) EE. Spyridon Baltsavias (Spiros) EE. Reona Otsuka (Leo) EE . Andrew Woo (Andy) EE. Previous Block Diagram. 4. 4. 4. 4. 4. 4. variable resistance. variable resistance. s witch signal.
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Final Project Review Team Vibraid April 2014
Vibraid Michael Balanov (Mike) EE SpyridonBaltsavias (Spiros) EE Reona Otsuka (Leo) EE Andrew Woo (Andy) EE
Previous Block Diagram 4 4 4 4 4 4 variable resistance variable resistance switch signal 5 different modules Processing done in software, everything else in hardware
Current Block Diagram Processing block absorbs Filtering module Filtering done digitally!
Reason behind Digital Filtering • Analog filters attenuated input signal • Extra amplification was required • Physical space limitation • 3 filters per microphone = total of 12 filter circuits • Additional space for extra amplification/active filter • Digital advantages • Ideal band cutoffs • No attenuation • Allows for easy combination of filters
Arduino Processing Changes • Optimized through low level coding to increase sampling rate • From 2.5kHz to around 14kHz rate for each microphone • Implemented an optimized FFT to determine frequencies received by the microphones • If fundamental frequency is inside desired band, pass signal for comparison • Block low-pass noise that was observed • Due to limited analog inputs, the Motor strength knob has been changed to a Motor strength switch
Final Comparator Logic Design Decided to implement SPL (amplitude) comparison instead of Time Delay estimation Time Delay could not be improved enough to meet the required specs SPL comparison met specs after purchasing better directional microphones
Demo Outline Frequency filtering demo Wearing the device – 4 way directionality
Frequency Filtering 3 switches: High, Mid, Low (-pass) Low band: 100Hz to ~300Hz Mid band: ~300Hz to 600Hz High band: ~600Hz to ~7000Hz Combination of bands possible
Digital Filtering Disadvantages • Sampling rate needs to be high enough (Nyquist rate) • Adds to processing time