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Advanced Detector Configuration for University Data Rates

This document outlines the configuration details for data rates and setups for the University of Arizona Micromegas Channels, including VMM2 counts, occupancy rates, readout data format, trigger data transmission, configuration considerations, and power requirements.

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Advanced Detector Configuration for University Data Rates

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  1. NSW Data Rates University of Arizona

  2. Micromegas Channels • Number of sides – 2 • Number of sectors – 16 • Number of layers per sector – 8 • Number of “panels” per sector – 4 • Number of channels per panel – 2048 • Total = 2M • Orthogonal view not yet considered

  3. VMM2 Count • Number of VMM2 / system – 32768 • Number of VMM2 / panel – 32 • Number of VMM2 / “4-pack” – 128 • “Baseline” thinking for us has 4 VMM2 / MMFE

  4. Rates • Data at 0.9e33 /cm2/s at 7 TeV • Estimate at R=100 cm is 15 kHz /cm2/s at 5e34 /cm2/s at 14 TeV

  5. Occupancy • Hits in smallest panel • 15 KHz / cm2 rate • 100 ns drift time with 5 mm gap • 50 cm x 100 cm approximate area of innermost panel • 7.5/2048 = 0.4% • 10 times less at R=400 cm

  6. Configuration • Number of e-links / GBT – 40 @ 80 MHz • Bandwidth is not an issue • Considerations are GBT – VMM2 connection and redundancy • Ideally redundancy in VMM2 (2 configuration inputs)

  7. Readout Data • L1A rate of 200 kHz (5 us) • Data - 6 bit address + 2 bit chip ID? + 12 bit time + 12 bit peak = 32 bits / hit • Number of hits / VMM2 @ 1% occupancy - ~ 2 (includes NN readout) • Number of bits / MMFE (4 VMM2) = 245 • Readout @ 160 MHz = 1.5 us • Considerations are GBT – VMM2 connection and redundancy

  8. Trigger Data • If sending all trigger data • 6 bit address + 1 bit DAV flag / 25 ns = 280 MHz / VMM2 • If reading non-zero trigger data • 4 hits x (6 bit address + 5 bit ID) / 25 ns = 1760 MHz / plane

  9. MMFE_4 Block Diagram SPI MOSI to VMM2_1 CONFIG SCA Slow Control ASIC to eport1 SPI MISO from VMM2_4 CONFIG BC_CLK, BC_CNT, NBR, Misc BC + SIGS TRIG/TKN ADDR L1 Accept TKN/DATA SPI CFG L1 Accept/TKN TTC Data @ 160 MHz from 2xGBT eport2,3 VMM2_1 64 Analog In Protection • 2xGBT provides redundancy. • BC distribution is provided from synchronized Reference Clock. • Eport4 can be input only • 4x160MHz eports == 1 group • 1 GBT == 10 groups == 10 MMFE • WC 10 MMFE * 4 eports * 160MHz = 6.4GHz • Can One SCA SPI drive 10 MMFE4 *4 VMM2? • Can SPI be changed to I2C on VMM2? • What are SCA and GBT power requirements? • Will VMM2 ASIC have eports, or will it need glue? • Do we need a VMM2 Chip ID? L1 Accept TKN/DATA BC + SIGS SPI CFG TRIG/TKN ADDR 64 Analog In VMM2_2 Protection BC + SIGS L1 Accept TKN/DATA TRIG/TKN ADDR SPI CFG VMM2_3 64 Analog In Protection L1 Accept TKN/DATA SPI CFG BC + SIGS TRIG/TKN ADDR VMM2_4 64 Analog In Protection L1 Data @ 160 MHz to 2xGBT eport2,3 L1 Accept Data 1.2V DC Trigger Rate @ 240 MHz *4 to ? TRIG/TKN/ADDR

  10. Integrating GBTs to a LAN Separate GBT from ROD: enables more freedom, less work, for ROD. Separation of DCS from DAQ. Philippe Farthouat interested as possibility for many experiments and detectors. Detailed specifications and prototyping work starting by: Niko Neufeld, LHCB, Jos and Lorne. See:http://lorne.web.cern.ch/lorne/IntegratingGBTs.pdf

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