Parallel Fault Simulation Using Verilog PLI

1. Parallel Fault Simulation Using Verilog PLI Sara Karamati CAD Lab, Department of electrical and computer engineering, university of Tehran

2. Outline • Fault Simulation • Parallel Fault Simulation • Parallelism Implementation • Parallel Fault Injection & Removal • A Case Study • Speed Up Analysis • Conclusion

3. Fault Simulation • Fault collapsing • For all faults • Fault injection • Simulation in presence of faults • Fault removal • Fault coverage

4. Parallel Fault Simulation • Collapse faults based on DUT • Provide Nf circuits, working in parallel ?!?! • While there is a fault • Inject Nf faults into Nf circuits ?!?! • Simulate all Nfcircuits simultaneously ?!?! • Compare golden model with Nffaulty circuits • Remove Nf faults • Coverage factor

5. Several techniques for reducing fault simulation time • The multiprocessor Fault Simulation Techniques[1]-[4]. • Test set partitioning • Fault list partitioning • Circuit partitioning • Parallel Fault Simulation Method Based on Structurally Synthesized BDDs (SSBDD) [8]. • Hierarchical Parallel Fault Simulation Method [10]

6. Parallel Fault Simulation Engine Problems • Specific Simulation Engines • Several Workstations • Unfamiliar from Designers Point of View • No Integration of HDL & Fault Simulation Specific Simulation Engine COST

7. Who Says “There is no free lunch?” • PLI Approach • No Specific Simulation Engine • Utilization of RTL CAD Tools • HDL & Fault Simulation Integration • The Same Steps as Serial Fault Simulation • Its Free, Why not use it?

8. Parallelism Implementation • Trivial solution • Generate Nf real circuits, using “generate” statement • Lots of PLI & tracing • More realizable solution • Pack Nf inputs of all Nf circuits into a vector • One single circuit, with vectorized inputs • A vectorizable library of components

9. Trivial Solution • Generation of ordinary DUT

10. More Realizable Solution • New Configured DUT

11. Configurable Components module and_n #(parameter n = 2, tphl = 1, tplh = 1, nf=3) (out,in); input [(n*nf)-1:0] in; output [nf-1:0]out; reg [nf-1:0]val; integer i; always@(in) begin val = in[nf-1:0]; for(i=1; i<n; i=i+1) begin val=val & in[(nf*i)+:nf]; end end assign out=val; endmodule

12. Parallel Fault Injection • Read Nf fault strings from fault list • While (counter < Nf) • Modify each string in order to match the vectorized circuit • char * str_modifier (…) • Inject modified fault into vectorized circuit • ParInjectFault ()

13. Parallel Fault Removal • While (counter < Nf) • Modify each string in order to match the vectorized circuit • char * str_modifier (…) • Remove modified fault from vectorized circuit • ParRemoveFault ()

14. Parallel Circuit Simulation • Simulate vectorized circuit • Nothing more !!! • Different bits of the inputs instead of inputs to different simulation runs • Different bits of the outputs instead of outputs of different simulation runs

15. A Sample Parallel Fault Simulation • The “c499” Benchmark as DUT • Fanout Insertion via New Components • 50 Parallel Faults, i.e. Nf =50 • Some Modifications to Testbench • ParFaultInjection.dll • Faster Simulation

16. C499 Parallel Fault Simulation module c499PSF #(parameter nf = 50); integer status[nf-1:0]; reg [nf-1:0] stuckAtVal; reg [500:0] wireName [nf-1:0]; … wire [nf-1:0]N724G,N725G,N726G,N727G,… … c499_fo #(nf)FUT(N1,N5,N9,N13,N17,N21,… … $ParInjectFault (nf, wireName[0], wireName[1], …, wireName[50], stuckAtVal[0], stuckAtVal[1], …, stuckAtVal[50]); … $ParRemoveFault( nf, wireName[0] , wireName[1], …, wireName[50]); …

17. Speed Up vs. Nf

18. Speed Up for ISCAS Benchmarks Nf=50

19. Conclusion • Fault Simulation Significance • Parallel Fault Simulation Engine, a Drawback • PLI Approach as a Free Lunch • Simulate Nf Circuits in Parallel • Parallelism via Vectorized Circuit • Inject & remove Nf Faults • Speed up Saturation over Nf • Speed up Analysis for ISCAS Benchmarks

20. References • [1] D. Krishnaswamy, E.M. Rudnick, J.H. Patel and P. • Banejee, " SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation," in Proc.VLSI Test Symposium 1997.  • [2] M. B. Amin and B. Vinnakota, “Data Parallel-Fault Simulation”, in IEEE Trans. VLSI Systems, vol. 7, no. 2, pp. 183-190, Jun. 1999.  • [3] Amit K. Varshney, Eric Skuldt, “High Performance Parallel Fault Simulation”, Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors, 2001.  • [4] Steven Parkes, PrithvirajBanerjee, Janak Patel, “A Parallel Algorithm for Fault Simulation based on PROOFS”, International Conference on Computer Design, 1995.  • [5] Raja Daoud, FusonOzguner, “Highly Vectorizable Fault Simulation on the Cray X-MP Supercomputer”, IEEE Transactions on Computer-Aided Design, December 1989.  • [6] S. Seshu, “On an improved diagnosis program”, IEEE Transactions on Electronic Computers, vol. 14, pp. 76–79, 1965. 

21. References • [7] M. Nadjarbashi, Z. Navabi and M. R. Movahedin, “Line Oriented Structural Equivalence Fault Collapsing” Proceedings of Workshop on Model and Test, Germany, 2000.  • [8] R. Ubar, S. Devadze, J. Raik and A. Jutman, “Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs”, 12th IEEE European Test Symposium (ETS), 20-24 May 2007, pp. 131 – 136.  • [9] H. Kyunghwan and L. Soo-Young, “A parallel implementation of fault simulation on a cluster of workstations”, IEEE International Symposium on Parallel and Distributed Processing, 14-18 April 2008, pp. 1-8.  • [10] S. Misera and H. T. Vierhaus, “FIT - A Parallel Hierarchical Fault Simulation Environment”, IEEE International Conference on Parallel Computing in Electrical Engineering (PARELEC), 7-10 Sept. 2004, pp. 289-294.

22. Thanks for Your Attention

23. Specific Simulation Engine vs. PLI Approach Cont.