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Design of Second-Order Bandgap Mixed-Mode Voltage Reference Circuit for Low Voltage Applications

Design of Second-Order Bandgap Mixed-Mode Voltage Reference Circuit for Low Voltage Applications. Rajarshi Paul Prof. Amit Patra Department of Electrical Engineering and Advanced VLSI Design Lab. IIT Kharagpur, India. 05/18/01 V4.3. Motivations.

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Design of Second-Order Bandgap Mixed-Mode Voltage Reference Circuit for Low Voltage Applications

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  1. Design of Second-Order Bandgap Mixed-Mode Voltage Reference Circuit for Low Voltage Applications Rajarshi Paul Prof. Amit Patra Department of Electrical Engineering and Advanced VLSI Design Lab. IIT Kharagpur, India 05/18/01 V4.3

  2. Motivations • First-order corrected References are not sufficient to meet the errors due to mismatches in layout and package effects. • Need for higher precision Reference for applications like Power and Data converters. • Substrate and supply noise require good PSRR behavior. • Low Power consumption and stable startup Circuit

  3. Novelties in the proposed circuit • Mixed-Mode topology for sub-bandgap voltage reference circuit. • Second-order temperature compensated circuit. • Low power consumption and good PSRR behavior using pseudo-supply. • Novel state-dependent startup circuit.

  4. Specification Targeted • Supply Voltage variation from 4-8V. • TC below 15 ppm/0C. • Sub-bandgap voltage reference. • Temperature Range from -40 0C to 120 0C. • PSRR < -15 dB • Line regulation < 0.2 % • 0.5 µm BiCMOS process

  5. Existing Solutions for sub-bandgap voltage reference circuit. • Using Resistor-divider. • Current-mode topology by Banba et.al. • Using weak-inversion operation of MOSFETs. • Using Dynamic-threshold MOSFETs.

  6. Proposed Schematic

  7. New Mixed Mode Topology • This topology complements the basic current mode topology with a voltage mode current ladder. • Voltage mode ladder offers the flexibility for individual compensation of the curvature nature of the bandgap voltage

  8. Proposed Scheme

  9. IPTAT2 Current

  10. First-order Indp Current • Rptat chosen to allow a • desired IPTAT current. • Rctat chosen for first- • order correction.

  11. TC RESULT • 1 mV variation. • TC = 14.5 ppm/0C • Temperature range from -40 to 120 0C.

  12. Line Regulation. Line regulation < 0.20% over 4 to 8V.

  13. PSRR Behavior and Start-up Circuit. • Use of Local rail by using Pseudo-supply. • Voltage headroom is an issue.

  14. PSRR RESULT PSRR < -13 dB.

  15. Start-up Circuit • A major issue for removing degenerate solutions. • State-dependent startup circuit used. • Designed to meet all process corners and cold-startup problems. Circuit thoroughly tested schematically using supply voltage ramp with slow slew-rate.

  16. Design of Trimming Resistor 1) Current Mirroring Mismatch Error. 2) Resistor Mismatch. 3) Resistor Tolerance . 4) Package Shift .

  17. Schematic Simulation Result

  18. Layout of the Chip • 0.5µ BiCMOS process. • Trimming of Rptat resistor. • Matching and general thumb-rules for correcting process variation effects considered. • Rpbase resistor used.

  19. Result

  20. Bandgap Circuit

  21. Schematic

  22. Result

  23. Test Results for 20 Parts and All Trim Codes A wide variation of 110 mV ( 10%) in magic voltage

  24. ΔV x 106 TC1= ppm/0C V25 x 160 slope x 106 TC2= ppm/0C Vavg x 160 (V25-Vmin) x 106 TCA= ppm/0C V25 x (25-(-40)) (Vmax-V25) x 106 TCB= ppm/0C V25 x (120-25) Different Definitions of Overall TC Vmax V25 V120 Vmin ΔV -40 25 Tx 120 TC3= TCA+TCB Temperature in 0C

  25. Trimming Method #1 • From test samples find the best trim-code for each part. • Find the magic voltage at room temp. which has the highest occurrence among the parts with the above trim-codes. This is the magic voltage for product parts. • For product parts, trim the bandgap voltage at room temp. to the above magic voltage.

  26. Step 1: Test Result for Best Trimcode Variation in each part over temperature < 4.5mV (25 ppm/0C)!!!! But a wide variation of 85mV ( 4%) in magic voltage

  27. Sample Test Data Trimmed Product Data Step 2: Finding the best Magic Voltage Trim to 1.150V magic voltage

  28. Step 3: Result of Trim Method1 Magic Voltage Variation over all parts < +/- 25 mV ( +/- 2.1%)

  29. Step 3: Result of Trim Method1 Magic Voltage Variation over all parts < +/- 20 mV ( +/- 2.5%)

  30. Trimming Method #2 • From all test samples find the best trim-code giving the least temperature variation of each part. • Find the trim code which as highest occurrence among the parts. This would be the trimming value in the design. • Chose the desired reference magic voltage. • For product parts, trim the reference output at room temp. to the desired magic voltage.

  31. Use this trim code for design Step 1,2: Frequency of Best Trim Code

  32. Step 3: Result of Triming Method 2. Magic Voltage Variation over all parts < +/- 11 mV ( +/- 1.3%)

  33. Comparision of th Results Sampled Data = 20

  34. Conclusion • A sub-bandgap voltage reference using a new topology is proposed. • Major Issues like higher-order temperature compensation, power supply rejection, stability of startup circuits has been explored. • Test results of the chip designed in pvip50 process presented. • Comparision of trimming methodology for post-fabrication optimization has been explored.

  35. Acknowledgement The authors would like to thank: Mr. Barry Culpepper, Mr. Faruk Nome, Mr. Bijoy Chatterjee and The Power Management Group at National Semiconductor Corp. USA. Prof. G.A Rincon-Mora, Georgia Institute of Technology. Prof. P.P.Chakraborty, CSE Dept., IIT Kharagpur.

  36. Thank You

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