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Process Compensated High Speed Ring Oscillators in Sub-Micron CMOS

Process Compensated High Speed Ring Oscillators in Sub-Micron CMOS. Xuan Zhang, Mustansir Mukadam, Ishita Mukhopadhyay, and Alyssa Apsel Cornell University Ithaca, NY USA. 12/12/2010. Outline. Introduction Related Work Proposed Solution Measurement Results Conclusion.

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Process Compensated High Speed Ring Oscillators in Sub-Micron CMOS

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  1. Process Compensated High Speed Ring Oscillators in Sub-Micron CMOS Xuan Zhang, Mustansir Mukadam, Ishita Mukhopadhyay, and Alyssa Apsel Cornell University Ithaca, NY USA 12/12/2010 CASFEST 2010, Athens, Greece

  2. Outline • Introduction • Related Work • Proposed Solution • Measurement Results • Conclusion

  3. Variability in Deep Sub-micron Nodes Line Edge Roughness (LER) Random Dopant Fluctuation (RDF) Source: L.T. Pang, et al., JSSC, 2009. Source: A. Asenov, et al., Async, 2008. Source: Intel Technology Journal, 2008. D2D – die-to-die WID – within die CESL – contact etch stop layer STI – shallow trench isolation

  4. Impact on Circuit Design • Dilemma for mixed-signal design • Increasing ft and fmax • Higher density integration • Better power efficiency • Higher variability • => yield loss • => design constraints Source: U.Mich, SODA Architecture, Micro, 2007. Source: A. Nieuwoudt, et al., DAC, 2005.

  5. Why High Speed Oscillators? • Ubiquitous in Integrated Circuits • High-speed I/O • Phase-locked loop • Low power transceiver • Wake-up radio • Uncertain IF architecture • Super-regenerative Source: N. Pletcher, et al., JSSC, 2009. Stability Area Power Phase Noise Accuracy Tuning Range Source: J. Bohorquez, et al., JSSC, 2009.

  6. Frequency Variation in Ring Oscillators • Highly susceptible to process variation • Implications to the system • Critical design constraints • Over-design • Sacrifice other specs Source: H. Masuda, et al., CICC, 2005. Chip-to-chip variation more than 20% Source: S. Drago, et al., TCAS-I, 2009.

  7. Outline • Introduction • Related Work • Proposed Solutions • Measurement Results • Conclusion

  8. Test Phase: Trim, Fuse & Calibrate • Accuracy and Flexibility • High quality external references • One-time or programmable • Cost is Catching Up • Automatic testing equipment • Built-in complexity • Sophisticated testing scheme • Testing time is a cost, need to minimize. Source: ITRS Road map report, 2001.

  9. Layout Phase: Lithography & Layout • Resolution Enhancement • Optical proximity correction • Off-axis illumination • Phase-shift mask • Only fixes one source of variation. • Layout Techniques • Common-centroid • Only improves local matching.

  10. Design Phase: Redundancy and Global Tuning • Global Tuning in Processors • Adaptive body bias (ABB) • Within-die ABB • Adaptive VDD • Off-chip crystal oscillator is needed. Source: J. Tschanz, et al. DAC 2005. • Redundancy and Re-configurability • Duplicate ADC stages • Novel coding in DAC • Multiple oscillator in PLL • Area and complexity penalty for high precision matching. Source: D. Daly, et al. JSSC 2009.

  11. Design Phase: Self-Compensated Circuits voltage, current, transconductance I=I1+I2: the addition current. I1, I2: negatively correlated. To engineer the correlation such that statistically ΔI1=-ΔI2, Vgs2 is generated by

  12. Design Phase: Feedback Loop • Negative Feedback in Circuits • Gain desensitization • Example: • Amplifier: gain matched to C1/C2 ratio • PLL: phase matched to reference • Since loop gain is unit-less, input and output share the same unit • Require high precision reference in the same domain. Source: B. Razavi, McGraw, 1997.

  13. Existing Low Variation Oscillators • External Frequency Reference • PLL regulated local oscillator • Post-process calibration • Extract timing from data • Fully-Integrated with No External Component • Novel structure as reference • (eg. thermal-diffusivity, silicon resonator ) • Relaxation oscillator • low power, low frequency (~KHz) • Ring Oscillator Source: C. Chan, JSSC, 2010. Source: S. Kashmiri, JSSC, 2010.

  14. Existing Low Variation Oscillators • External Frequency Reference • PLL, calibration, data timing extraction • Fully-Integrated with No External Component • Novel device as reference • Relaxation oscillator • Ring oscillator • sensing threshold and tuning Vctrl • Approximation only valid for ~MHz. • constant gm with big capacitor • Power hungry to sustain high gm for high frequency Source: K. Sundaresan et al, JSSC 2006. How to design a low-power, low-cost, low-variation on-chip oscillator at GHz?

  15. Outline • Introduction • Related Work • Proposed Solutions • Measurement Results • Conclusion

  16. Process Compensation Loop • Basic System Concept • => Convert frequency to a DC value • => Compare it to a DC reference • => Generate the correction to Vctrl • Eliminate off-chip frequency reference. • Perform the comparison at lower rate. Perform frequency  voltage conversion (current charging a capacitor) Transform error signal  correction voltage

  17. Comparator-Based Loop Functional model for each block Comparator Charge Pump Frequency accuracy: Static oscillation period: VREF>>σREF, σCP,off, ACP>>1

  18. Frequency Sensor • Process-Invariant Block • Low variation current source • Charge sharing between big cap Sample Share Reset

  19. Comparator, VCO and Charge Pump • Comparator • diff-pair • large matching input • Charge pump • IUP=IDN=150µA • IUP and IDN matched when VCP,out=VDD/2 • VCO • 3-stage current-starved ring oscillator • 780MHz~5.6GHz

  20. Loop Dynamic and Stability • Two Phases in Loop Dynamic • Bang-bang region • large initial freq offset • binary comparator output • Near locking • continuous-time approximation Root Locus (3 poles) Freq acquisition with different initial offsets in bang-bang region Step Response

  21. Switched Capacitor-Based Loop To improve stability, the correction should be proportional to the error signal. Thus ideally, we want This can be realized by switched capacitors. error represented by charge difference (c) correction (a) initialization (b) comparison

  22. Frequency Accuracy If the finite gain and offset of the opamp are considered, the update equation needs to be modified: Static oscillation period: Frequency accuracy: Again, variations in IREF and C1 dominate.

  23. Outline • Introduction • Related Work • Proposed Solutions • Measurement Results • Conclusion

  24. Calibrated with External Current Source • Single-point current calibration • baseline case • current-biased RO • 8.7% variation • process compensated • 2.6% variation due mostly to cap tolerance • 3.3x improvement • Post-process calibration process can be simplified

  25. Fully On-Chip with Addition-Based Current Source • Full integrated on-chip • baseline case • current-starved RO with fixed Vctrl • 17.7% variation • process compensated • freq correlated with the addition-based current • 4.6% variation • 3.8x improvement • Frequency accuracy can be improved without external component.

  26. Multiple Wafer-Run Results Switched Cap. Based Loop Multiple wafer-runs have been taped out in 90nm CMOS. Consistent improvement is observed from more than 200 chips.

  27. Temperature and Supply Voltage Sensitivity To the first order, fosc is proportional to • C is usually constant with T and VDD • IREF is provided by the addition-based current source • 90ppm/oC temperature sensitivity • linear with VDD, if biased generated from a VDD divider. Measured (168ppm/oC) Simulated (IREF and fosc vs VDD)

  28. Temperature and Supply Voltage Sensitivity • Designed for above 2GHz range • Area<0.01mm2 • Power: 1.95mW • Verified by chips from 2 lots • Taped out in 90nm CMOS

  29. Conclusion • Investigated the validity of a process compensation scheme based on feedback loop that uses DC blocks (current source) as low variation “ruler-on-chip” to calibrate high speed oscillators. • Demonstrated two implementations of the proposed process compensation loop in: 1) a comparator-based system and 2) a switched capacitor-based system, and provided detailed discussion on their frequency accuracy and loop dynamics. • Presented comprehensive measurement results showing: 1) with single point current calibration, better than 2.6% frequency accuracy can be achieved; 2) without calibration and off-chip component, 4.6% frequency accuracy can be achieved– a 3.8x improvement over the baseline case. • Similar reduced sensitivity to temperature and supply voltage has been simultaneously accomplished.

  30. Reference [1] N. M. Pletcher, S. Gambini, and J. Rabaey, “A 52μW Wake-Up Receiver With -72 dBm Sensitivity Using an Uncertain-IF Architecture”, IEEE Journal of Solid State Circuits, vol. 44, No. 1, pp. 269-280, Jan. 2009. [2] K. R. Lakshmikumar, “Analog PLL Design with Ring Oscillators at Low-Gigahertz Frequencies in Nanometer CMOS: Challenges and Solutions”, IEEE Tran. on Circuits and Systems-II: Express Briefs, vol. 56, No. 5, pp. 389-393, May 2009. [3] H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki, “Challenge: Variability Characterization and Modeling for 65- to 90-nm Process”, Proc. IEEE Custom Integrated Circuits Conference, pp. 593-599, Sep. 2005. [4] H. Chen, E. Lee and R. Geiger, “A 2 GHz VCO with Process and Temperature Compensation,” Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 569-572, May 1999. [5] S. Drago, D. Leenaerts, B. Nauta, F. Sebastiano, K. Makinwa, and L. Breems, “A 200 µA Duty-Cycled PLL for Wireless Sensor Nodes in 65nm CMOS”, IEEE Journal of Solid State Circuits, vol. 45, No. 7, pp. 1305-1315, Jul. 2010. [6] M McCorquodale, G. Carichner, J. O'Day, S. Pernia, S. Kubba, E. Marsman, J. Kuhn, and R. Brown, “A 25-MHz Self-Referenced Solid-State Frequency Source Suitable for XO-Replacement”, IEEE Trans. on Circuits and Systems I: Regular Papers, May 2009. [7] C. Chan, K. Pun, K. Leung, J. Guo, L. Leung, and C. Choy, “A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders”, IEEE Journal of Solid State Circuits, vol. 45, No. 3, pp. 587-599, Mar. 2010. [8] M. Kashmiri, M. Pertijs, K. Makinwa, “A Thermal-Diffusivity-Based Frequency Reference in Standard CMOS with an Absolute Inaccuracy of 0.1% from -55oC to 125 oC”, Digest of International Solid-State Circuits Conference, pp. 74-75, Feb. 2010. [9] D. Ruffieux, F. Krummenacher, A. Pezous, and G. Spinola-Durante, “Silicon Resonator Based 3.2 µW Real Time Clock With ±10ppm Frequency Accuracy”, IEEE Journal of Solid State Circuits, vol. 45, No. 1, pp. 224-234, Jan. 2010. [10] U. Denier, “Analysis and Design of an Ultralow-Power CMOS Relaxation Oscillator”, IEEE Tran. on Circuits and Systems-I: Regular Papers, vol. 57, No. 8, pp. 1973-1982, Aug. 2010. [11] K. Sundaresan, P. E. Allen and F. Ayazi, “Process and temperature compensation in a 7-MHz CMOS clock oscillator,” IEEE Journal of Solid State Circuits, vol. 41, No. 2, pp. 433-442, Feb. 2006. [12] A. Pappu, X. Zhang, A. Harrison, and A. Apsel, “Process Invariant Current Source Design: Methodology and Examples,” IEEE Journal of Solid State Circuits, vol. 42, No. 10, pp. 2293-2302, Oct. 2007. [13] X. Zhang and A. B. Apsel, “A Low Power, Process-and-Temperature- Compensated Ring Oscillator with Addition-Based Current Source”, TCAS-I, in print. 2010.

  31. Thank You. Xuan (Silvia) Zhang MustansirMukadam IshitaMukhopadhyay

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