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A Modern CMOS Process

A Modern CMOS Process. Observe parasitic capacitances! Cap from gate to channel. Cap from gate sidewall to source or drain. Cap from bottom of drain diffusion to well. Cap from sidewall of drain to well (small with STI). Dual-Well Trench-Isolated CMOS Process. Epi on p+ substrate shown.

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A Modern CMOS Process

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  1. A Modern CMOS Process • Observe parasitic capacitances! • Cap from gate to channel. • Cap from gate sidewall to source or drain. • Cap from bottom of drain diffusion to well. • Cap from sidewall of drain to well (small with STI). Dual-Well Trench-Isolated CMOS Process • Epi on p+ substrate shown. • P-substrate (no epi) is more common • Less expensive • Better for mixed-signal, esp RF. • More vulnerable to latch-up Figure from website of Digital Integrated Circuits, 2nd ed.

  2. Dynamic Behavior of MOS Transistor

  3. Gate Capacitance Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off To each Cgs entry in the table, add Cgso; to each Cgd entry, add Cgdo. Cgdo = CGDO∙W, Cgso = CGSO∙W

  4. Diffusion Capacitance Channel-stop implant Side wall Source W N D Bottom x Side wall j Channel L Substrate N S A Drawing assumes LOCOS isolation. Obsolete, but consistent with many examples in text. Formula is ok.

  5. Junction Capacitance

  6. Interconnect: Wires connecting transistors http://www.avii-ic.com/Figure5r.gif Interconnect has parasitic resistance and capacitance

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