VLSI Fabrication Technology

1. VLSI Fabrication Technology 1

2. Figure A.1 Silicon ingot and wafer slices.

3. Figure A.2 (a) An 8-pin plastic dual-in-line IC package, (b) A 16-pin surface mount package.

4. (e) n+ diffusion (mask #4) (a) Define n-well diffusion (mask #1) (f) p+ diffusion (mask #5) (b) Define active regions (mask #2) (g) Contact holes (mask #6) (c) LOCOS oxidation Figure A.3 A typical n-well CMOS process flow.

5. (h) Metallization (mask #7) (d) Polysilicon gate (mask #3) Figure A.3 (Continued)

6. Figure A.4 Cross-sectional diagram of an n- and p-MOSFET.

7. Figure A.5 Cross sections of resistors of various types available from a typical n-well CMOS process.

8. Figure A.6 Interpoly and MOS capacitors in an n-well CMOS process.

9. Figure A.7 A pn junction diode in an n-well CMOS process.

10. Figure A.8 Cross-sectional diagram of a BiCMOS process.

11. Figure A.9 A lateral pnp transistor.

12. Figure A.10 p-Base and pinched p-base resistors.

13. Figure A.11 Cross-sectional diagram of a symmetrical self-aligned npn SiGe heterojunction bipolar transistor (HBT).

14. Figure A.12 A CMOS inverter schematic and its layout.

15. Figure A.13 Cross section along the plane AA¢ of a CMOS inverter.

16. Figure A.14 A set of photomasks for the n-well CMOS inverter. Note that each layer requires a separate plate: (a), (d), (e), and (f) dark-field masks; (b), (c), and (g) clear-field masks.