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A 65nm CMOS Fully Integrated 31.5dBm Triple SFDS Power Amplifier dedicated to W‑CDMA Application

A 65nm CMOS Fully Integrated 31.5dBm Triple SFDS Power Amplifier dedicated to W‑CDMA Application. Y. Luque 1 , N. Deltimple 1 , E. Kerherve 1 , D. Belot 2 1 IMS Laboratory, University of Bordeaux, IPB/ENSEIRB-MATMECA, IMS laboratory, 33405 Talence cedex, Fance

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A 65nm CMOS Fully Integrated 31.5dBm Triple SFDS Power Amplifier dedicated to W‑CDMA Application

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  1. A 65nm CMOS Fully Integrated 31.5dBm Triple SFDS Power Amplifier dedicated to W‑CDMA Application Y. Luque1, N. Deltimple1, E. Kerherve1, D. Belot2 1IMS Laboratory, University of Bordeaux, IPB/ENSEIRB-MATMECA, IMS laboratory, 33405 Talence cedex, Fance 2STMicroelectronics, Minatec, Grenoble, France yohann.luque@ims-bordeaux.fr

  2. Outline • Introduction • Context • State of the art • Targeted standard • Triple Stacked Folded pseudo-Differential Structure (SFDS) PA • Triple SFDS circuit • Triple SFDS behavior • 65 nm CMOS Triple SFDS PA • Overall PA • CW simulation • HPSK simulation • Conclusion and future works

  3. Outline • Introduction • Context • State of the art • Targeted standard • Triple Stacked Folded pseudo-Differential Structure (SFDS) PA • Triple SFDS circuit • Triple SFDS behavior • 65 nm CMOS Triple SFDS PA • Overall PA • CW simulation • HPSK simulation • Conclusion and future works

  4. Telecommunication market • Increase the interactive services in mobile phones while limiting the fabrication cost and the phone size. • Reduce die area of circuits in order to implement new services • Reduce the cost of each chip • To level the eventual disappearance of old CMOS technologies GSM (2G) EDGE (2.5G) UMTS (3G) HSPA (3.5G) LTE (4G) WLAN WWAN WiFi GPS WPAN WMAN Bluetooth Zigbee WiMAX, UWB MBWA Proposition : Design a PA using 65 nm CMOS technology dedicated to UMTS standard

  5. UMTS (3G) • UMTS (Universal Mobile Telecommunication System) • Pout(max) = 24 dBm (the most widespread) • Freq = 1.92-1.98 GHz Tx (2Mbps) • Modulation schemes (QPSK, HPSK) Power challenge High output power for long distance communication with 65 nm CMOS technology

  6. W-CDMA • W-CDMA (Wideband Code Division Multiple Access) • HPSK Modulation (Hybrid Phase-Shift Keying)  non constant modulation envelope • Requirement on Pout  From -20dBm to 24dBm • Requirements on linearity : • ACPR1=-33dBc at +/- 5MHz • ACPR2=-43dBc at +/- 10MHz • HD3<40dBc Linearity challenge • optimize the linearity-efficiency trade-off • use a structure allowing to high gain to avoid a third stage (linearity-gain trade-off)

  7. 65 nm CMOS technology 130 nm MW Low backend More resistive 250 nm 130 nm 65 nm CMOS backend BiCMOS backend • decrease the quality factor of passive devices • increase electro-migration matters • increase capacitive parasitic and resistive issues • RF signal losses through the bulk Reduction of back-end leads to:

  8. 65 nm CMOS PA state of the art high BVDS transistors Process option (cost) High die area Distributed Active Transformer (DAT) Proposition : Design of elementary topology with low BVDS transistors and without DAT

  9. Outline • Introduction • Context • State of the art • Targeted standard • Triple Stacked Folded pseudo-Differential Structure (SFDS) PA • Triple SFDS circuit • Triple SFDS behavior • 65 nm CMOS Triple SFDS PA • Overall PA • CW simulation • HPSK simulation • Conclusion and future works

  10. Triple SFDS overview VDSM2 VDSM3 VDSM1 Input Output Triple SFDS schematic Small signal equivalent circuit

  11. SFDS versus differential cascode SFDS SFDS increases simultaneously the OCP1, the PAE and the Pmax Diff cascode

  12. Outline • Introduction • Context • State of the art • Targeted standard • Triple Stacked Folded pseudo-Differential Structure (SFDS) PA • Triple SFDS circuit • Triple SFDS behavior • 65 nm CMOS Triple SFDS PA • Overall PA • CW simulation • HPSK simulation • Conclusion and future works

  13. Overall PA • Requirements: • OCP1 = 27 dBm to be linear until 24dBm (back-off = 3dB) • BVDS = 1.8V Triple SFDS • Linearity, power Differential Cascode • Gain Matching Matching Matching Differential Cascode Triple SFDS

  14. CW simulation results BW_3dB= 25%

  15. HPSK simulation results HSPK simulation with ADS analogRF ACLR1 results according to Pout Constelation ACLR respected until 23 dBm with an EVM of 5%

  16. Without DAT With DAT Comparative table * High BVDS transistors [FRI08]-3.3V [WAN08]-6.2V

  17. Outline • Introduction • Context • State of the art • Targeted standard • Triple Stacked Folded pseudo-Differential Structure (SFDS) PA • Triple SFDS circuit • Triple SFDS behavior • 65 nm CMOS Triple SFDS PA • Overall PA • CW simulation • HPSK simulation • Conclusion and future works

  18. Conclusion • Challenge to design a CMOS PA dedicated to UMTS application. • Demonstration of a simulated PA constrained by stringent restrictions on low BVDS active device. • Validation of a new topology using low BVDS transistors & without DAT. • Achievement of a Pmax= 31.5dBm OCP1=27.5dBm at 1.9GHz with simulated 65nm CMOS technology provided by STMicrolectronics DK. • ACLR is respected until 23 dBm (EVM=10%) • Efficiency enhancement technique (dynamic biasing) • Layout achievement and measurements Future works

  19. Thanks for your attention

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