ECE 448: Spring 12 Lab Midterm Exam Review

ECE 448: Spring 12Lab Midterm Exam Review

Agenda for today Part 1: Detailed discussion of a selected midterm from Spring 2011. Part 2: Review & discussion of common mistakes made by students in Lab 1-3 Part 3: Lab demos and grading

Selected midterm from Spring 2011

Common mistakes made by students in Lab 1-3

Mistakes in Lab 1 • Assert condition: • The message is written when the condition is FALSE. assert initial_value <= max_value report "initial value too large" severity error;

Use of Test vector table and Output Comparison Test Vector Table: CONSTANTtest_vector_table: test_vectors:= ( (operation => AND_OP, a=>'0', b=>'0', y=>'0'), (operation => AND_OP, a=>'0', b=>'1', y=>'0'), (operation => AND_OP, a=>'1', b=>'0', y=>'0'), (operation => AND_OP, a=>'1', b=>'1', y=>'1'), (operation => OR_OP, a=>'0', b=>'0', y=>'0'), (operation => OR_OP, a=>'0', b=>'1', y=>'1'), (operation => OR_OP, a=>'1', b=>'0', y=>'1'), (operation => OR_OP, a=>'1', b=>'1', y=>'1'), (operation => XOR_OP, a=>'0', b=>'0', y=>'0'), (operation => XOR_OP, a=>'0', b=>'1', y=>'1'), (operation => XOR_OP, a=>'1', b=>'0', y=>'1'), (operation => XOR_OP, a=>'1', b=>'1', y=>'0'), (operation => XNOR_OP, a=>'0', b=>'0', y=>'1'), (operation => XNOR_OP, a=>'0', b=>'1', y=>'0'), (operation => XNOR_OP, a=>'1', b=>'0', y=>'0'), (operation => XNOR_OP, a=>'1', b=>'1', y=>'1') ); Providing Input: test_operation <= test_vector_table(i).operation; test_a <= test_vector_table(i).a; test_b <= test_vector_table(i).b; Comparing Output: IFtest_y /= test_vector_table(i).y THEN error_cnt := error_cnt + 1;

Mistakes in Lab 2 • Choosing proper libraries: • USE ieee.numeric_std.all; • USE ieee.std_logic_unsigned.all ; • USE ieee.std_logic_signed.all; • Opcodes: • Rotation right with Carry by 2 • Arithmetic Shift Right by 3 with Rounding • Variable Rotation Right • Variable Logic Shift Left • Variable Arithmetic Shift Right with Rounding • Variable Logic Shift Right

Difference between Dataflow, Structural and Behavioral coding styles • Dataflow: Concurrent statements • Structural: Components and Interconnects • Behavioral: Processes • Difference between Combinational and Sequential logic • Combination: Not dependent on Clock • Sequential: Dependent on Clock (Registers, Shift registers. Counters, State machines)

Mistakes in Lab 3 • Use of Generics • Shift Register

Variable left shift

Use of Generics and For Generate:Variable 16-bit rotator TYPE array1 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0); TYPE array2 IS ARRAY (0 to 3) OF STD_LOGIC_VECTORS(15 DOWNTO 0); SIGNAL Al : array1; SIGNAL Ar : array2; BEGIN Al(0) <= A; G: FOR i IN 0 TO 3 GENERATE ROT_I: fixed_rotator_left_16 GENERIC MAP (L => 2** i) PORT MAP ( a => Al(i) , y => Ar(i)); MUX_I: mux2to1_16 PORT MAP ( w0 => Al(i), w1 => Ar(i), s => B(i), f => Al(i+1)); END GENERATE; C <= Al(4); END variable_rotator_16;

D(0) D D D D Q Q Q Q Shift Register With Parallel Load Load D(3) D(1) D(2) Sin Clock Enable Q(3) Q(2) Q(1) Q(0)

Enable N N D Q Load Sin shiftn Clock N-bit shift register with parallel load (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shiftn IS GENERIC ( N : INTEGER := 8 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable : IN STD_LOGIC ; Load : IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END shiftn ;

Enable N N D Q Load Sin shiftn Clock N-bit shift register with parallel load (2) ARCHITECTURE behavioral OF shiftn IS SIGNAL Qt: STD_LOGIC_VECTOR(N-1 DOWNTO 0); BEGIN PROCESS (Clock) BEGIN IF rising_edge(Clock) THEN IF Enable = ‘1’ THEN IF Load = '1' THEN Qt <= D ; ELSE Qt <= Sin & Qt(N-1 downto 1); END IF; END IF ; END PROCESS ; Q <= Qt; END behavior al;

Lab 4 Demos

ECE 448: Spring 12 Lab Midterm Exam Review