1 / 23

Loran-C Receiver

Loran-C Receiver. ECEN 4610 Capstone CDR. Team Deathstar: Christopher Birschbach Matthew Hayman Matthew Anderson Christina Corner Erin Mowbray. October 5, 2004. Budget System Diagram Subsystem Functionality Hardware/Schematics Parts List Software Design Progress since PDR

ajaxe
Download Presentation

Loran-C Receiver

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Loran-C Receiver ECEN 4610 Capstone CDR Team Deathstar: Christopher Birschbach Matthew Hayman Matthew Anderson Christina Corner Erin Mowbray October 5, 2004

  2. Budget System Diagram Subsystem Functionality Hardware/Schematics Parts List Software Design Progress since PDR Future Goals and Deadlines Milestone 1 Milestone 2 Expo Division of Labor Questions/Comments Agenda

  3. Budget

  4. Block Diagram

  5. Outline of Approach • The system will consist of the following subsystems: • Antenna Receiver • Analog-to-digital converter • Motorola 68HC11 processor • Memory • FPGA • Serial Interface • PC • Power

  6. Antenna/Receiver • AM Antenna • 8th Order Butterworth Filter (MAX274B) (This portion of the project will continue when the filters from Maxim arrive.)

  7. Signal Processing Unit Part List

  8. Processor Schematic

  9. FPGA Design • Chip select • State machine • Counter

  10. FPGA Schematic

  11. FPGA – Chip Select

  12. Software Design • FPGA: • Input • Digital Loran-C signal • Output • Counter Data • Processor: • Input • Counter Data • Output • Time delays • PC: • Input • Time delays • Output • Latitudinal and Longitudinal coordinates

  13. Software Design • Initial Test Code

  14. Software Design

  15. Schematic Design Initial Wire wrapped board completed Basic Processor Functionality Basic FPGA Functionality Basic RAM Functionality Progress since PDR

  16. Project Timeline

  17. Future Deadlines • Milestone 1 – 10/26 • Milestone 2 – 11/16 • Open-Lab Expo – 12/9

  18. Milestone 1 • Date: October 26th • Parts completed: • Completed Wiring on Vector Board • Antenna/Filtering –Clean signal • Sampling by A/D converter completed • Order first PCB

  19. Milestone 2 • Date: November 16th • Parts Completed: • Functioning PCB • State machine on FPGA working • Communication between the Processing Unit and Antenna/Receiver.

  20. Capstone Expo • Working Loran-C Receiver • Functionality between all 3 Subsystems: Antenna/Receiver, Processing Unit, & PC • Working Serial Interface

  21. Extra Features • These will be added if time permits at the end of the semester. • Portable Power Supply • LCD Display

  22. Division of Labor • Matt A • Power • Memory interface • Microprocessor Programming • Chris B • PC programming • Microprocessor programming • User’s Manual • Christy C • Antenna/Filtering • Verilog Design • User’s Manual • Matt H • Antenna/Filtering • PCB • Microprocessor Programming • PC programming • Erin M • Verilog Design • User’s Manual • PC interface

  23. Questions/Comments

More Related