1 / 10

2/17/2010 Iowa State University EE492 - Senior Design II

May 2009 Senior Design Group #27 Test Chip For Electrothermal Reliability Research Design Team: Karl Peterson , Emmanuel Owusu, and Joshua Ellis Advisor: Dr. Randall Geiger | Client: VLSI Thermal Research Group. 2/17/2010 Iowa State University EE492 - Senior Design II. Project Plan.

aladdin-reed
Download Presentation

2/17/2010 Iowa State University EE492 - Senior Design II

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. May 2009 Senior Design Group #27Test Chip For ElectrothermalReliability ResearchDesign Team: Karl Peterson , Emmanuel Owusu, and Joshua EllisAdvisor: Dr. Randall Geiger | Client: VLSI Thermal Research Group 2/17/2010 Iowa State University EE492 - Senior Design II

  2. Project Plan Original plan was tape-out in 0.5µ process on January 21st Problems: aggressive schedule, more modern process desirable In early January, finally arranged an end-of-January tape-out in collaboration with students at Tatung University in Taiwan Fabrication provided through a Taiwanese organization in a 0.18µ process New problems: limited pin-count and area

  3. Original Project Design

  4. Reduction of Analog Circuitry • Pin count was insufficient for the advanced, multi-cell control we had planned • PDK was accessible only weeks before the deadline  no time to develop ADC • Basically had to be a test chip for sensors only • 6 sensor designs developed by VLSI research group (two contributed by design team members) • Analog mux still needed to be implemented to minimize pin count (only 8 pins available)

  5. Reduction of Digital Circuitry • Analog mux control (important to reduce pin count) • Only one supply pin  digital could not be run continously • Trimming functionality included for 3 of the 6 sensors • No ADC and no IDAC  significantly reduced digital functionality • Because the PDK was delivered very late, no digital flow was developed • Registers and de-coders built by hand!

  6. Final layout – submitted 1/31 ISU Portion

  7. Final layout – submitted 1/31 MUX Decoder Power Switches Shift Register Sensors 1-3 Sensors 4-6 MUX Switches

  8. Sample test results

  9. New Plan Still want to implement original design with full functionality Fabrication options are being explored (hopefully the same process can be used to salvage some blocks) Target tape-out is April 15th If samples arrive from the first design before then, testing results can guide second design Schedule is still very aggressive!

  10. New Schedule – Upcoming Deadlines IDAC done – March 16th(Josh) ADC done – March 16th(Karl) Digital flow with new PDK – March 20th(Eman) Final re-specification – March 20th(All) Update documentation – April 1st(All)

More Related