Restructuring for delay optimization

1. Restructuring for delay optimization Speaker : Guo-Jhu Huang Advisor : Chun-Yao Wang 2009.03.13

2. Outline • Introduction • Idea • Flow Chart • Future work

3. Introduction • Given a timing constraint (usually the clock period) • the combinational circuit must meet its timing constraint to work correctly.

4. Idea • Only sensitizable paths contribute to the delay of a circuit • To check these longest paths if they are sensitizable paths

5. Idea • Exact sensitizable path side-input [nc,-] [cv, ≧t] side-input [nc, ≦t] g g f [cv,t] f [nc,t] side-input [nc,-] [cv, ≧t] side-input [nc, ≦t]

6. Idea • Apply IRRA to remove the wire on the critical path • IRRA - Select a target wire and a destination gate • Which wire as a target wire is the better choice? • Which gate as a destination gate is the better choice?

7. Idea SMAs SMAs … … • (wt,gd) affects the longest rectified network path gdg(SMA) gdg(SMA) gd EAN ERN …

8. Idea • If (wt,gd) is the target wire and the destination gate • Observation 1 : • Observation 2 :

9. Idea • The longest path of rectified network • Estimation (assume 2-input gate allowed)

10. Idea • If (wt,gd) meets the observation condition, we apply IRRA whose target wire is wt and destination gate is gd.

11. Flow Chart Find candidate critical path Check the candidate critical paths if they is sensitizable paths IRRA If exist critical paths? Estimate the (wt,gd) Yes Yes If exist (wt,gd)? No END No

12. Future work • Study more papers