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Delay and Power Optimization with TSV-aware 3D Floorplanning

Delay and Power Optimization with TSV-aware 3D Floorplanning. M. A. Ahmed and M. Chrzanowska-Jeske Portland State University, Oregon, USA. ISQED 2014. Outline. Introduction Electrical Characteristics of 3D Interconnect 3D-Interconnect Electrical Performance TSV Aware 3D Floorplanning

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Delay and Power Optimization with TSV-aware 3D Floorplanning

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  1. Delay and Power Optimization with TSV-aware 3D Floorplanning M. A. Ahmed and M. Chrzanowska-Jeske Portland State University, Oregon, USA ISQED 2014

  2. Outline • Introduction • Electrical Characteristics of 3D Interconnect • 3D-Interconnect Electrical Performance • TSV Aware 3D Floorplanning • Experimental Results • Conclusions

  3. Introduction • 3D technology facilitates reduction in wirelength by vertically stacking dies. • TSVs are used to connect inter-die signals, and the RC value of a single TSV depends on TSV dimensions, technology and used materials. • It is crucial to consider RC values of TSVs early in the design phase to evaluate and optimize electrical performance of 3D ICs.

  4. Introduction • This paper proposed a TSV-aware 3D floorplanning tool that concurrently places TSV islands with circuit blocks.

  5. Electrical Characteristics of 3D Interconnect • TSV Capacitance • CTW: coupling capacitance between a TSV and wires surrounding the TSV • CTT: coupling capacitance between TSVs

  6. Electrical Characteristics of 3D Interconnect • TSV Resistance • The expression for TSV resistance is given by: • is the resistivity of the material • lTSV is the height of TSV • ATSV is area of the TSV

  7. Electrical Characteristics of 3D Interconnect • Wire Resistance and Capacitance

  8. Electrical Characteristics of 3D Interconnect • Wire Resistance and Capacitance

  9. 3D-Interconnect Electrical Performance • Interconnects Delay

  10. 3D-Interconnect Electrical Performance • Interconnects Delay • The difference between the interconnect delay in two cases will be significant if TSV delay is large. • The floorplanners without TSV delay will treat these cases similarly.

  11. 3D-Interconnect Electrical Performance • Interconnects Power Consumption

  12. TSV Aware 3D Floorplanning

  13. Experimental Results

  14. Experimental Results

  15. Experimental Results

  16. Experimental Results

  17. Experimental Results

  18. Conclusions • This paper presented and discussed delay and power results of a novel TSV-aware 3D floorplanning flow with TSV islands.

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