Execution Cycle

1. Execution Cycle

2. Outline • (Brief) Review of MIPS Microarchitecture • Execution Cycle • Pipelining • Big vs. Little Endian-ness • CPU Execution Time IF IF IF IF ID ID ID ID EX EX EX EX MEM MEM MEM MEM WB WB WB WB

3. MIPS Microarchitecture • Recall the datapath for the lw (load word) command

4. MIPS Microarchitecture • The first step was to fetch the instruction

5. MIPS Microarchitecture • fetch the instruction

6. MIPS Microarchitecture • The next step was to decode the instruction

7. MIPS Microarchitecture • decode the instruction

8. MIPS Microarchitecture • Next, execute the instruction

9. MIPS Microarchitecture • execute the instruction

10. MIPS Microarchitecture • Next, access memory (if necessary)

11. MIPS Microarchitecture • Finally, write back to a register

12. MIPS Microarchitecture • write back to a register

13. MIPS Microarchitecture • Just described classic 5-stage execution cycle • Fetch • Decode • Execute • Memory • Write Back • 5-stage execution cycle typical of RISC machines • RISC is easier to explain • CISC is more complicated… • x86 is CISC

14. Outline • (Brief) Review of MIPS Microarchitecture • Execution Cycle • Pipelining • Big vs. Little Endian-ness • CPU Execution Time IF IF IF IF ID ID ID ID EX EX EX EX MEM MEM MEM MEM WB WB WB WB

15. Execution Cycle (aka Instruction Cycle) IF – Instruction Fetch ID – Instruction Decode EX -Execute MEM – Memory WB- Write Back

16. Execution Cycle - Fetch IF • Send the program counter (PC) to memory • fetchthe current instruction from memory • Update the PC • PC = PC + 4 • (since each instruction is four bytes) ID EXE MEM WB

17. Execution Cycle - Decode IF • Figure out type of instruction (e.g., load, add, etc.) • Based on “opcode” • Determine registers involved • aka “operands” • Get things “setup” for execution • Control Unit sets appropriate pins ID EXE MEM WB

18. Execution Cycle - Execute IF • ALU operates on operands prepared during decode • ALU performs function based on instruction type • Arithmetic (add, subtract, …) • Logic (equivalence, negation, …) ID EXE MEM WB

19. Execution Cycle - Memory IF • If instruction is LOAD, • Read data from effective memory address • Effective memory address computed during EXE • If instruction is STORE, • Write data from register to effective memory address • Effective memory address computed during EXE • MEM is an OPTIONAL execution stage • Memory access does not always occur ID EXE MEM WB

20. Execution Cycle – Write Back IF • Write results “back” to a register • Result type depends on instruction • Results could be from: • ALU computation -or- • Memory access (i.e., load) ID EXE MEM WB

21. Execution Cycle – Fetch IF • The execution cyclethen repeats… • The next instruction is already indicated by PC • Recall that PC set to PC + 4 during previous fetch ID EXE MEM WB

22. Outline • (Brief) Review of MIPS Microarchitecture • Execution Cycle • Pipelining • Big vs. Little Endian-ness • CPU Execution Time IF IF IF IF ID ID ID ID EX EX EX EX MEM MEM MEM MEM WB WB WB WB

23. Pipelining • It’s laundry day, and you have to complete the following tasks: • Wash white clothes in washing machine • Dry white clothes in dryer • Wash color clothes in washing machine • Dry color clothes in dryer • Wash athletic clothes in washing machine • Dry athletic clothes in dryer

24. Pipelining • Would you do the following? • I.e., Wait for each load to washanddry before starting next? dry colors dry whites wash colors wash whites dry athletic wash athletic time

25. Pipelining • Heck no!! • What a waste of time!! • What do you do instead? dry colors dry whites wash colors wash whites dry athletic wash athletic time

26. Pipelining • Overlap: wash one load while another is drying dry whites wash whites wash colors dry colors wash athletic dry athletic time

27. Pipelining • Do more things at once… dry whites wash whites wash colors dry colors wash athletic dry athletic time

28. Pipelining • Complete tasks in less time… FREE TIME!!

29. Pipelining • Can this be applied to the execution cycle? • Yes!! • Fetch the next instruction while decoding the current instruction? • Decode the next instruction while executing the current instruction? • … IF IF ID ID EX EX MEM MEM WB WB

30. Pipelining • Typical 5-stage pipeline of RISC CPU • 5thinstruction is being fetched while 1stinstruction is being written back • There are much deeper and fancier pipelines… IF IF IF IF IF ID ID ID ID ID EX EX EX EX EX MEM MEM MEM MEM MEM WB WB WB WB WB

31. Pipelining • Typical 5-stage pipeline of RISC CPU • 9clock cycles to complete5instructions

32. Pipelining • Without pipelining • 25clock cycles to complete 5instructions … IF IF ID ID EX EX MEM MEM WB WB

33. Pipelining • There are several things that can disrupt a pipeline • Called hazards • E.g., What happens if the nextinstruction depends on the result of the current instruction?

34. Pipeline Hazards • Three types of hazards • Control hazard • Data hazard • Structural hazard

35. Pipeline Hazards: Control • Control Hazard • Occurs when pipelining branches (e.g., if statements) • … or other instructions that change the PC ???

36. Pipeline Hazards: Data • Data Hazard • Occurs when an instruction tries to use data before it’s available • For example: 1: R1 <- R2 + R3 2: R4 <- R1 + R5 • Contents in R1 (register 1) may have been loaded for instruction#2 beforeinstruction#1 has finished. • Several types of data hazards…

37. Pipeline Hazards: Data • Data Hazard 1: R1 <- R2 + R3 2: R4 <- R1 + R5 1: 2: IF IF ID ID EX EX MEM MEM WB WB R1 used in instruction #2’s executionbefore instruction #1 writes back

38. Pipeline Hazards: Structural • Structural Hazard • Occurs when one hardware component is needed by two (pipelined) tasks at same time • Example: read from andwrite to memory at the same time • Fetch an instruction from memory while writing data to memory • Hence why instruction and data memory are separated

39. Pipelining: Solutions • Ways to minimize pipeline hazards • Stall • Flush • Out-of-order execution • Forwarding • Bypassing • Branch prediction • … • Beyond the scope of this course… • Learn about / master pipeline hazards

40. Break Time!!! I don’t fish, but this likes nice…

41. Outline • (Brief) Review of MIPS Microarchitecture • Execution Cycle • Pipelining • Big vs. Little Endian-ness • CPU Execution Time IF IF IF IF ID ID ID ID EX EX EX EX MEM MEM MEM MEM WB WB WB WB

42. Big vs. Little Endian • Some important jargon: 0x97 46 AB 07 1001 0111 0100 0110 1010 1011 0000 0111 MSB: Most Significant Bit LSB: Least Significant Bit

43. Big vs. Little Endian 0x97 46 AB 07 1001 0111 0100 0110 1010 1011 0000 0111 Most Significant Byte Least Significant Byte MSB can stand for most significant bit OR byte LSB can stand for least significant bit OR byte

44. Big vs. Little Endian • Endian refers to the ordering of bytes for multiple byte words • How the bytes are stored in memory • How the bytes are interpreted • Whether the MSB comes “first” or “last” • Whether the LSB comes “first” or “last” MSB - Most Significant Byte LSB - Least Significant Byte

45. Big Endian • Most significant byte stored at smallestaddress • Least significant bytestored at largest address 0x97 46 AB 07

46. Little Endian • Most significant byte stored at largest address • Least significant bytestored at smallest address 0x97 46 AB 07

47. Example • Store 0x46 A0 B7 FF using: Big Endian Little Endian

48. Example • Store 0x46 A0 B7 FFusing: Big Endian Little Endian

49. Outline • (Brief) Review of MIPS Microarchitecture • Execution Cycle • Pipelining • Big vs. Little Endian-ness • CPU Execution Time IF IF IF IF ID ID ID ID EX EX EX EX MEM MEM MEM MEM WB WB WB WB

50. CPU Execution Time