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Execution Cycle

Execution Cycle. Dynamic DLX (much simpler) 2 FP multiply (10 EX cycles) 1 FP add (2 EX cycles) 1 FP divide (40 EX cycles) 1 integer unit (1 EX cycle). Instruction stream. 3 Load/Buffers. FU count down. 3 FP Adder R.S. 2 FP Mult R.S. Clock cycle counter. Tomasulo Example.

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Execution Cycle

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  1. Execution Cycle • Dynamic DLX (much simpler) • 2 FP multiply (10 EX cycles) • 1 FP add (2 EX cycles) • 1 FP divide (40 EX cycles) • 1 integer unit (1 EX cycle)

  2. Instruction stream 3 Load/Buffers FU count down 3 FP Adder R.S. 2 FP Mult R.S. Clock cycle counter Tomasulo Example

  3. Tomasulo Example Cycle 1

  4. Tomasulo Example Cycle 2 Note: Can have multiple loads outstanding

  5. Tomasulo Example Cycle 3 • Note: registers names are removed (“renamed”) in Reservation Stations; MULT issued • Load1 completing; what is waiting for Load1?

  6. Tomasulo Example Cycle 4 • Load2 completing; what is waiting for Load2?

  7. Tomasulo Example Cycle 5 • Timer starts down for Add1, Mult1

  8. Tomasulo Example Cycle 6 • Issue ADDD here despite name dependency on F6?

  9. Tomasulo Example Cycle 7 • Add1 (SUBD) completing; what is waiting for it?

  10. Tomasulo Example Cycle 8

  11. Tomasulo Example Cycle 9

  12. Tomasulo Example Cycle 10 • Add2 (ADDD) completing; what is waiting for it?

  13. Tomasulo Example Cycle 11 • Write result of ADDD here? • All quick instructions complete in this cycle!

  14. Tomasulo Example Cycle 12

  15. Tomasulo Example Cycle 13

  16. Tomasulo Example Cycle 14

  17. Tomasulo Example Cycle 15 • Mult1 (MULTD) completing; what is waiting for it?

  18. Tomasulo Example Cycle 16 • Just waiting for Mult2 (DIVD) to complete

  19. Faster than light computation(skip a couple of cycles)

  20. Tomasulo Example Cycle 55

  21. Tomasulo Example Cycle 56 • Mult2 (DIVD) is completing; what is waiting for it?

  22. Tomasulo Example Cycle 57 • Once again: In-order issue, out-of-order execution and out-of-order completion.

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