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14.1 A Multicycle Implementation. Figure 14.1 Single-cycle versus multicycle instruction execution. Unified cache (data cache and instruction cache)
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14.1 A Multicycle Implementation Figure 14.1 Single-cycle versus multicycle instruction execution.
Unified cache (data cache and instruction cache) • Inst Reg, Data Reg: When a word is read out, it must be kept for all remaining cycles in its execution to generate the control signals properly. • Register x, y, z: hold information between cycles. • Execution of one instruction: 3 to 5 cycles
x4 x4 Figure 14.3 Key elements of the multicycle MicroMIPS data path.
14.2 Clock Cycle and Control Signals We assume the following latencies for the basic steps in instruction execution Clock cycle is 2ns. That is clock frequency is 500MHz.
Table 14.1 Control signals for the multicycle MicroMIPS implementation.
Table 14.2 Execution cycles for the multicycle MicroMIPS implementation.
14.3 The Control State Machine This loop continues until a syscall is executed with 10 in $v0. This instruction terminates program execution
Control state sequences for various MicroMIPS instruction classes: ALU-type 0,1,7,8 Load word 0,1,2,3,4 Store word 0,1,2,6 Jump/branch 0,1,5
Figure 14.5 State and instruction decoders for multicycle MicroMIPS.
Control signals determined by control state, op, and fn. ALUSrcX=ControlSt2 ControlSt5 ControlSt7 RegWrite=ControlSt4 ControlSt8 Auxiliary control signals: asssubInst=addInst subInst addiInst logicInst=andInst orInst xorInst norInst andiInst oriInst xoriInst ALU Control Signals: Add/Sub=ControlSt5 (ControlSt7subbInst) FnClass1=ControlSt7’ addsubInst logicInst FnClass0=ControlSt7 ( logicInst sltInst sltiInst) LogicFn1=ControlSt7 ( xorInst xoriInst norInst) LogicFn0=ControlSt7 ( orInst oriInst norInst)
PC control Signals: JumpAddr=syscallInst PCSrc1=ControlSt0 ControlSt5 (beqInst bneInst bltzInst) PCSrc0=ControlSt0 ControlSt5 jrInst PCWrite=ControlSt0 ControlSt5 [jInst jrInst jalInst syscallInst (ALUZero beqInst) (ALUZero’ bneInst) (ALUout31 bltzInst)]
14.4 Performance of the Multicycle Design Clock rate is 500MHz. The performance = 500/4.04=123.8MIPS. This is virtually the same as the 125 MIPS performance of our single-cycle implementation. With the instruction latencies being more varied, the multicycle design would have led to a performance gain over the single-cycle implementation.
14.5 Microprogramming • Control state machine resembles a program that has instructions, branching, and loops. Such a hardware program is called a microprogram, and its basic steps are called microinstructions. • Within each microinstruction, different actions, such as asserting the MemRead control signal, or setting ALUFunc to “+”, are called microorders. • Advantages: • Makes the hardware simpler, more regular, less dependent on the details of ISA. • Easy to correct error by simply changing microprograms. • Machine is microprogrammable (even by user). • Drawback: • It is slow. Each MicroMIPS instruction requires 3-5 ROM accesses.
Sequence control: 00: Advance to the next microinstruction in sequence by in incrementing μPC. 01 and 10: Allow branching to occur depending on OPcode field in machine instruction being executed. 11: Go to microinstruction 0 (corresponding to state 0 in state machine) Figure 14.6 Possible 22-bit microinstruction format for MicroMIPS.
Dispatch table: translate OPcode into micrSequence control: Dispatch table 1: Correspond to multiway branch from cycle 2 to cycle 3. Dispatch table 1: Correspond to multiway branch between 3 and 4. Figure 14.7 Microprogrammed control unit for MicroMIPS.
Table 14.3 Microinstruction field values and their symbolic names:the default value for each unspecified field is the all-0s bit pattern.
Figure 14.8 The complete microprogram for MicroMIPS.The comments on the right show that each microinstruction corresponds to a state or substate in the control state machine of Figure 14.4.
Figure 14.9 Alternate MicroMIPS microinstructions representing states 7 and 8 in the control state machine of Figure 14.4.
Exceptions ALU operation leads to overflow. Opcode field holds a pattern that does not represent a legal operation. Cache error-detecting code checker deems an accessed word invalid Sensor or monitor signals a hazardous condition Exception handler: OS routine that handles exception. When exception occurs, the control is forced to transfer to exception handler. 14.6 Dealing with Exceptions
Cause Reg: save a code for exception EPC( exception program counter): save PC-4 mfc0 (similar to mfc1): examine the contents of registers in Coprocessor 0.
