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Test Setup for PHOBOS Hybrid/Module Testing at MIT. Pradeep Sarin 31 July 98. Test Setup. Power Supply V det. Sr-90 Src. Power Supply +6V. Power Supply -6V. 26 pin cable. Function: Logic : Use on-board logic or External NIM logic to time and route TRIG, HOLD, CLK, TESTP etc signals.
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Test Setup for PHOBOS Hybrid/Module Testing at MIT Pradeep Sarin 31 July 98
Test Setup Power Supply Vdet Sr-90 Src Power Supply +6V Power Supply -6V 26 pin cable Function: Logic : Use on-board logic or External NIM logic to time and route TRIG, HOLD, CLK, TESTP etc signals. National InstrumentsSCB Box 50 pin cable Module (Type 1) 20 pin cable Transition Card Function: a) Simple re-routing of wires b) Jumpers for temperature sensor Scintillator Computer Cable Repeater Card Function: a) Distribute Vdet ; ±6V to Vss and Vdd b) Control current and voltage params. c) Route control signals from PC to Hybrid. NIM Logic Trigger LabVIEW PC
Calibration Algorithm for LabVIEW Switch Test Mode OFF Take ~300 Pedestal Events. Calculate avg pedestal for each channel Zero input signal, digitize output Switch Test Mode ON Send Test Pulse into VA chip with level=Vcal Send HOLD signal after Tpeak ~ (1.2 to 2.0s) Acquire and DigitizeAnalog Output of VA chip Do “Signal Conditioning” Increment Vcal
Calibration Timing (Not to Scale!) Test Mode OFF ON TRIG Trigger Disabled (Random Trigger) Into PC/Logic 1 2 3 n+1 CLK (25 kHz) From PC Digitize 10s Test Pulse 20s From PC/Logic Precisely adjustable Tpeak 1.2 - 2.5 s HOLD 15-30s From PC/Logic VA Analog O/P To ADC PED Chan 0 PED Chan 2 PED Chan 1 VA Reset
Source Test Algorithm for LabVIEW Take ~300 Pedestal Events. Calculate avg pedestal for each channel Zero input signal, digitize output Trigger on Scintillator Signal Send HOLD signal after Tpeak ~ (1.2 to 2.0s) Acquire and DigitizeAnalog Output of VA chip Do “Signal Conditioning” Move Radiation Source?
Source Test Timing (Not to Scale!) External Trigger Disabled Scintillator TRIG Into PC/Logic Precisely adjustable Tpeak 1.2 - 2.5 s HOLD From PC/Logic Example Signal held in any one channel VA Analog O/P To ADC ADC_Start TRIG to PC SHIFT_IN to VA Can be Zero 1 2 3 N+1 CLK From PC/Logic LabVIEW VI Digitize N Channels VA Reset
“Signal Conditioning - 1” Pedestal Subtraction • pedestal for each channel is average of ~300 pedestal events • measured initially, before the test begins 0 127 0 127 0 127
“Signal Conditioning - 2” Common Mode Noise Correction • Calculate Avg signal in all Empty channels, leaving out the channels that have a real hit SIGCMN • Subtract SIGCMN from signal in each channel SIGCMN 0 127 0 127
“Signal Conditioning - 3” Pedestal Drift Correction • Has been noticed in testing of Type 1 modules (caveat - no handle on temperature stability) • What may happen: • Pedestal Subtraction and CMN correction gives noisier signals -Real pedestals are different from measured pedestals 0 127
“Signal Conditioning - 3 (contd)” Currently to correct for pedestal drift we can do: Landau Signal Gaussian Noise 0 Signal (ADC) distribution (after Pedestal subtraction and CMN) • The Zero mean of the Gaussian noise drifts because of drift in pedestals • Add the value of the mean (weighted by a factor) to each channel’s pedestal every ~50 events
Capabilities Data is automatically written to ORACLE database • Calibration Tests 1. Gain per Channel 2. Electronically dead channels 3. Pedestals per channel • Source Tests1. Pedestals per channel 2. Signal/Noise Ratio for Sr-90 source 3. Signal Distribution 4. Hit profile in detector 5. Noise v/s channel with and without CMN correctionCan’t do yet : Interrupted trace lines, but ideas...
