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Ramp up at 4V/sec

Ramp up at 4V/sec. 25 Nov. 2003 T. Tsuboyama (KEK). Bias ramping up/down speed. We are thinking to increase the ramp up speed of bias voltage from 2V/sec to 4V/sec. (From 1V/sec to 2 V/sec for both positive and negative side.)

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Ramp up at 4V/sec

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  1. Ramp up at 4V/sec 25 Nov. 2003 T. Tsuboyama (KEK)

  2. Bias ramping up/down speed • We are thinking to increase the ramp up speed of bias voltage from 2V/sec to 4V/sec. (From 1V/sec to 2 V/sec for both positive and negative side.) • In case of SVD1, the voltage level of N-side strips are at +80V while the VA1 input was at the ground level. The increase of the detector bias voltage directly charge the coupling capacitors and a large current flows into VA1 input circuit. In SVD2, the floating power supply system changed the situation. • The purpose of this report is to check the effect of ramping up to the VA1 preamplifier.

  3. The model circuit Cd • The model circuit of SVD2 front end is given as follows. It consists of a PIN diode, a bias power supply (Vbias), a detector capacitance for several sensors (Cd = 100pF), AC coupling capacitor (Cc = 100pF), VA1 input is assumed to be virtual ground. In this report I-VA1, the current though, Cc is evaluated under several assumptions. • Nakano and Tsuboyama confirmed the bias voltage from the Kenwood power supply increases at time smoothly. • For simplicity, the PIN diode is assumed to be a 40 GW resistor, which draws 2 nA leakage current at 80V bias voltage. Vbias Vbias Cc I-VA1 2 nA I diode 80V Vdiode

  4. Simple calculation Rdiode Cd • At ramping speed of d(Vbias)/dt = 4V/sec, and assuming a stable current, d(I_VA1)/dt=0, I_VA1 can be expressed as I_VA1=4V/sec*(Rbias/Rdiode)*Cc =4*(20x106)/(40x109)(100x10-12 ) A =200 fA • If the feed back resistor in VA1 is 20MW, the VA1 amplifier output swings by Vout=(200x10-15 )x(20x106)= 4 mV, which is enough in the dynamic range of the preamplifier. V1 Vbias Rbias I-VA1 0.4pF 20MW Simplified VA1 preamplifier

  5. Cd Rdiode V1 Vbias Cc Rbias I-VA1 SPICE simulation-I • The transient current at the start and stop of the ramping was simulated by the SPICE simulation code. Vbias, V1 and I_VA1are shown as function of time (0 to 23 sec). • At start/stop of ramping, V1 suffers a ~0.008 V offset due to charging / discharging of Cd. As a result, about 0.8pC of impulse charge enters VA1. Except these spikes, I_VA1 is 200 fA as calculated previously. A charge of 0.8pC results in 2V preamplifier output assuming a 0.4pF feed back capacitor. 2V is out of the dynamic range of the preamplifiers. Vbias V1 0.8pC I-VA1 dV/dt=4V/sec 200fA 20sec 0.008V

  6. Cd RL Rdiode CL V1 Cc Rbias Vbias I-VA1 SPICE simulation-II • Those spikes are due to the sudden start/ stop of the Vbias ramping. In the real circuit, low pass filters are inserted to the bias line in order to reduce noise. A simulation was done with a low pass filter (RL= 100kW and CL=1 mF) as shown in the right figure. • The shape of V1 is rounded and I_VA1 is reduced from impulse charge of 0.8pC to a decaying ~8pA current (160mV at the preamplifier output). 8pA Vbias V1 I-VA1 200fA

  7. Summary • The ramping speed of bias voltage can be 4V/sec (or faster) if necessary. • Owing to floating power supply scheme, the voltage to the AC coupling capacitors is always small. • The Kenwood power supply ramps up Vbias smoothly. • Several calculation was done to understand the effect of ramping speed of 4V/s. • In steady state, the current into VA1 input is 200fA that results in 4mV at the preamplifier output. • About 0.8 pC charge is expected at start/stop of ramping. However a 100 msec low pass filter at bias power supply reduces the pulse to ~8 pA decaying current, which is enough less than the preamplifier saturation. • In fact, PIN diodes have larger capacitance at lower bias voltages. However VA1 operation conditions are kept well even at 10 times larger transient current.

  8. Appendix: SPICE Opus v1 3 0 pwl(-1 0 1 0 21 80 30 80) r0 3 1 100k r1 1 2 40G r2 2 0 20meg c0 1 0 1u c1 1 2 100p c2 2 0 100p .end • This is for the first time I ever tried SPICE simulation. • SPICE Opus is a product of University of Ljubljana. • Downloaded from http://fides.fe.uni-lj.si/spice/ I forget how I found this cite. • After installation, I prepared the circuit file. and entered several commands at the prompt. Welcome to Program: SpiceOpus (c), version: 2.2 Light -> source bias.cir -> save @c2[i] all -> tran 0.001 23 -> plot v(3) -> plot v(1) -> plot @c2[i]

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