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NGR: Next Generation Router

NGR: Next Generation Router. Initial Design Review Shahzad Ali Xia Chen Brendan Howell Yu Zhong. Specifications. Minimum 64 port OC-48, aggregate capacity of 160Gbps, Fair Queuing. Extra features RED MPLS, QoS Multicast Scalability (higher port density). Overall Design. 16 Cards.

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NGR: Next Generation Router

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  1. NGR: Next Generation Router Initial Design Review Shahzad Ali Xia Chen Brendan Howell Yu Zhong

  2. Specifications • Minimum • 64 port OC-48, aggregate capacity of 160Gbps, Fair Queuing. • Extra features • RED • MPLS, QoS • Multicast • Scalability (higher port density) 18-757 Initial Design Review

  3. Overall Design 16 Cards Switch One port on a Line card Transceiver Cell buffer Scheduler + FQ Routing table Framer Network processor 18-757 Initial Design Review

  4. Components • Input Port processing (IPP) • Buffers • Switch Scheduling • Output port processing • Fair Queuing 18-757 Initial Design Review

  5. Input Port Processing • Line termination and data link processing • Break variable length packet into fixed length • Lookup routing information • Process packets at "line speed” i.e. close to 5 million routing lookup per second. • Do simple IP packet processing functions • Decrease TTL, Checksum etc. • MPLS or Hardware Filters 18-757 Initial Design Review

  6. Possible Solutions for IPP • Transceiver for line termination and PHY processing • HFCT-5402D by Agilent (HP) • VSC8140 by Vitesse • Framer for fixed size cells • VSC9112 by Vitesse • Network Processor • IXP1200 by Intel (Level One) • APP1200 and APP1400 by Agere • Generic micro-processor 18-757 Initial Design Review

  7. Where to Queue? • Input port • Does not require high fabric speedup. • OPP can be done at reasonable speeds • Difficult to do output scheduling (FQ) • Output port • Easy to schedule packets on the link (FQ) • Fabric and OPP have to have high speedup. 18-757 Initial Design Review

  8. Buffers • Our initial decision: • Buffer packets on the input port • Handle FQ at the input port (somehow) • Use standard SDRAM for buffers • PC-100 10ns access latency • Dimension buffer by simulation • Buffers for each input port. 18-757 Initial Design Review

  9. Switch Scheduling • We will simulate with various scheduling mechanisms including Multicast schemes. • iSLIP, RR, FCFS, TARTAR (for multicast) • Virtual Output Queues to avoid HOL • Nominal Fabric speedup and priority classes. • Implement both Drop-tail and RED buffer schemes. • Local delivery of packets on the same line card. 18-757 Initial Design Review

  10. Switch Fabric • Shoot for 1024x1024 but backup is 64x64 • Vitesse VSC836 takes too long to configure!! • 13cycles x 40ns = 520ns (1.9M Frames/sec) • Use AMCC S2018 17x17 in a 3-stage CLOS network. • Other options? 18-757 Initial Design Review

  11. Output Port Processing and Scheduling • Basic de-framing and physical level processing. • FQ discipline • WFQ • W2FQ • How do we do this with input buffering? • What level of buffering do we require at the output ports? 18-757 Initial Design Review

  12. Plan of Action • Decide on IPP and Network Processor. • Concentrate on switch fabric choice. • Analyze switch scheduling schemes. • Try to implement FQ with input port buffers. • Implement RED and Drop Tail. • Develop a simulator for the switch. • Experimentally determine the buffer size. 18-757 Initial Design Review

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