CPE/EE 428, CPE 528 Testing Combinational Logic (5)

1. CPE/EE 428, CPE 528 Testing Combinational Logic (5) Department of Electrical and Computer Engineering University of Alabama in Huntsville

2. Test Generation: The Podem Algorithm • What you know • The basic pieces of automatic test generation (ATG) • justification, propagation, implication, etc. • D-frontier • J-frontier • The D algorithm • What you don’t know • A better way — Podem • Today • Podem VLSI Design II

3. Test Generation: The D Algorithm Decorate design with all known values. Check for inconsistencies. if (imply_and_check() == FAIL) return FAIL if (error not at primary output) { if (D-frontier == Ø) return FAIL repeat { select an untried gate (G) from D-frontier c = controlling value of G assign c’ to every input of G with value x if (D-Alg() == SUCCESS) return SUCCESS } until all gates from D-frontier tried return FAIL} if (J-frontier == Ø) return SUCCESS select a gate G from the J-frontier c = controlling value of G repeat { select an input (j) of G with value x, assign c to j if (D-Alg() == SUCCESS) return SUCCESS assign c’ to j /* reverse decision*/ } until all inputs of G are specified return FAIL Push D to a primary output Once at primary output, justify all values needed to have D on the primary output VLSI Design II

4. j a g b k c f d i h e From Last Time… all x’s c=1, b=1 0 0 Decision Tree D’ h=1 1 1 c-sa0 D D’ j=0 D 0 a=1 1 d=0 decisions implications comments activate fault, unique D drive c=1,b=1,g=f=D’ h=1 i=D prop through i. j,k=Df; h=Jf a=1 j=D’, k=1 prop through j. Df = null. backtrack (a = x) j=0 a=0, k=D prop through i, fault at output d=0 justify h VLSI Design II

5. 1 0 D x x x x 1 0 D-frontier New concept to add • x-path • The D-frontier in the circuit below is hopeless. • There is no path to a primary output • An x-path is a circuit path along which all of the gate outputs have value x • If a gate in the D-frontier does not have at least one x-path to a primary output, the D cannot propagate to the output through this gate. • Don’t bother considering this gate for propagation • Drop it from the D-frontier (however, it may come back) VLSI Design II

6. Testing Digital Systems: Podem • Podem — Path-oriented decision making • Only uses forward implication • manipulates primary inputs directly — very goal oriented • No J-frontier or consistency check • since only the primary inputs are specified with values there is no inconsistency • the values might not be correct (i.e. the ones you want), but the implied values in the circuit are always consistent • Basic iterative flow • determine an objective • e.g. justifying a line or propagating a D • find a primary input to control the line or the propagation • set primary input and do forward implication • is everything cool? yes, no? VLSI Design II

7. PODEM Algorithm • PODEM – Path-Oriented DEcision Making algorithm • solves the problem of reconvergent fanout and allows multipath sensitization • Four basic steps: Objective, Backtrace, Implication, D-frontier • Objective • Pick an objective to set a node to a value • Backtrace • Backtrace to a PI and set it to a value that will help meet the objective • Implication • simulate the network to calculate the effect of fixing the value of PI. If there is no possibility of sensitizing a path to a PO, then retry by reversing the value of PI that was set in step 2 and simulate again. • D-frontier • Update D-frontier and return to step 1. Stop if the D-frontier reaches a PO. VLSI Design II

8. objective is justifying fault site to v’ objective is propagating fault along D-frontier to primary output Podem: determining an objective • Determining an objective • Given: we want to test line l s-a-v or propagate a fault to a primary output • There are only two objectives that can result Objective() if (line l is an x) return (l, v’) select gate G from D-frontier select input j from G having value x c = controlling value of G return (j, c’) • In both cases — • the objective is to justify a line — a line and value are returned VLSI Design II

9. Podem: the difference • Given an objective we must find a primary input to control to meet it • With the D algorithm, we didn’t look for PIs • Rather the D-alg put c’ on the other x inputs of the gate and assumed that it will work out later • Backtrace — • The objective is to justify a line to a certain value • step backward through gates until a PI is found • at each gate, select a gate input to follow • only keep track of inversions, no values assigned • return a primary input and the value to set it to • setting the PI to the value is not guaranteed to work! VLSI Design II

10. Podem: Backtrace Backtrace (k, vk) v = vk while (k is a gate output) { i = inversion of k select an input (j) of k with value x v = v  i k = j } return (k, v) while we’re not at a PI Determine what the input should be based on the inversion. Step backward All this does is find a PI and a value to set it to VLSI Design II

11. e … c f a d b Podem: Backtrace • Backtrace example — set f to 1 • Select in alphabetical order … • Are these values for primary inputs enough?, OK? • need to do forward implication and further checking • i.e. they may fanout and block the D-frontier f=1 VLSI Design II

12. 0 make this a 1 Podem: Backtrace • Another example: VLSI Design II

13. success — error is at PO, or we got another gate from the D-frontier and (recurse, recurse, …) got error to PO. Podem: the main algorithm Podem { if (error at primary output) return SUCCESS — you win, party time if (test not possible) return FAIL (k, vk) = Objective() (j, vj) = Backtrace (k, vk) imply (j, vj) if (Podem == SUCCESS) return SUCCESS imply (j, v’j) if (Podem == SUCCESS) return SUCCESS imply (j, x) return FAIL } Pick a gate from D-frontier or activate fault Find an input “test not possible” D-frontier == , or is expected to become  VLSI Design II

14. success — error is at PO, or we got another gate from the D-frontier and (recurse, recurse, …) got error to PO. Podem: the main algorithm Podem { if (error at primary output) return SUCCESS — you win if (test not possible) return FAIL (k, vk) = Objective() (j, vj) = Backtrace (k, vk) imply (j, vj) if (Podem == SUCCESS) return SUCCESS imply (j, v’j) if (Podem == SUCCESS) return SUCCESS imply (j, x) return FAIL } Oops, forward implications failed. Assign complement to input Oops, another failure. Probably D-frontier went east. VLSI Design II

15. h d’ d i s-a-1 j n e’ e k g a b c l f f’ m Testing Digital Systems: Podem VLSI Design II

16. h d’ d i s-a-1 j n e’ e k g a b l f f’ m Decision Tree An example 1 a = 0 0 Objective PI assignment Implications Comments a_branch = 0 a = 0 h = 1 D-frontier becomes {g} a_branch = D’ VLSI Design II

17. h d’ d i s-a-1 j n e’ e k g a b l f f’ m Decision Tree An example a = 0 1 b = 1 1 0 D’ c = 1 1 0 1 d = 1 D 0 1 D’ 1 e = 0 e = 1 Objective PI assignment Implications Comments k = 1 e = 1 e’ = 0, j = 1 D-frontier becomes {m, n} k = D’, n = x reverse decision VLSI Design II

18. h d’ d i s-a-1 j n e’ e k g a b l f f’ m Decision Tree An example a = 0 1 b = 1 1 0 D’ c = 1 1 D 0 1 d = 1 D 0 1 D’ c 1 1 e = 0 e = 1 0 1 D’ f = 1 Objective PI assignment Implications Comments l = 1 f = 1 f’ = 0, l = 1 m = D’, n = D Party time! VLSI Design II

19. j a g b k c f d i h e Another example G-sa1 G OBJ, PI implications comments VLSI Design II

20. define fault model X select target fault no more faults: done generate test for target — 100 fault simulate discard detected faults Summarizing the process set of faults for circuit X X X X X X X 1 X X 0 X X 0 VLSI Design II

21. Podem Summary • Summary and comparison to D • More of a direct approach • “what PIs can I wiggle to reach my objective” • backtracking arises only to change a primary input’s value. In the D algorithm, any gate input inconsistency could cause a backtrack. There are fewer PI’s than gate inputs! • Inconsistency doesn’t happen (from backtrace) • always going forward from primary inputs • however, setting inputs can cause x-path to output to go away • No J-frontier • Simplified recursive state changes • state in this algorithm is the PI values • everything else can be calculated through forward implication • Original comparison data showed faster runtimes. • Progression of techniques from D —> Podem VLSI Design II

22. which one? … repeat { select an untried gate (G) from D-frontier c = controlling value of G assign c’ to every input of G with value x if (D-Alg() == SUCCESS) return SUCCESS } until all gates from D-frontier tried return FAIL} … Selecting gates and inputs • D and Podem run for a long time • What can be done to improve the run time? • consider the “select one input” and “select one gate” • one path might be better than another VLSI Design II

23. a b … a b Controllability • Illustrative examples • Controllability — A measure of how difficult is it to justify a line justify this to a zero Obviously, b is more controllable than a. Obviously b, has fewer side-effects than a and may lead to fewer problems with reconvergent fanout. justify this to a zero Can controllability be quantified? VLSI Design II

24. a a Observability • Illustrative examples • Observability — A measure of how difficult it is to propagate a value to a primary output? • Includes costs for controllability because some lines “need justified” What’s the cost of observing a? What’s the cost of observing a? Can observability be quantified? VLSI Design II

25. a b f c Controllability Notation: Cv(l) is the cost of setting line l to v. • Two situations • The cost of setting f to 0 is the minimum of the costs of setting each of the inputs to 0 C0(f) = min{ C0(a), C0(b), C0(c) } • The cost of setting f to 1 is the sum of the costs of setting all of the inputs to 1 C1(f) = C1(a) + C1(b) + C1(c) VLSI Design II

26. Controllability Notation: Cv(l) is the cost of setting line l to v. • Generally • In terms of controlling value c and inversion value i • Consider the case where one of the inputs has controlling value c: Cci(f) = min{ Cc(a), Cc(b), Cc(c) } Gate output • Consider the case where all of the inputs must have non-controlling value c’ Cc’i(f) = Cc’(a) + Cc’(b) + Cc’(c) Gate output VLSI Design II

27. 1 a f b How is this applied? • Approach • The cost of setting an input is defined as 1 • Proceed from the inputs to the line in question. • The cost of setting f to 0 — C0(f) = min{C1(b), C1(a)} • The cost of setting a to 0 ? What inputs are needed to justify a to 0? VLSI Design II

28. f a b Controllability • Well, there are some anomalies • What’s the cost of setting f to1? C1(f) = C1(a) + C1(b) C1(b) = C0 (a) C1(f) = C1(a) + C0 (a) • But that’s impossible and the cost should be infinity • OK, it’s off-the-wall, but maintain perspective! • the point is that these methods consider only the structure • the cost of “doing all of the logic” to figure them out is high • higher than doing a bad job of “selecting a gate” • we don’t want the cost of selecting the correct path to be greater than the penalty for picking the wrong path VLSI Design II

29. a f … b c r … q s … Observability • Back to the AND gate • What’s the cost of observing a? • you need to control b and c to one • you need to observe f • Thus: O(a) = C1(b) + C1(c) + O(f) • How about a fanout from a stem? • the cost of observing a stem is the minimum of observing its branches O(q) = min{ O(r), O(s) } VLSI Design II

30. a Observability • Approach • The cost of observing a primary output is defined to be 0 • The circuit is traversed backward from the outputs Assuming a = D, what values will be at the POs? PO PO Let’s say this is the D frontier — which way do we go? VLSI Design II

31. a Cost of Testability • Can we calculate how hard it is to test a fault? Testability — the cost of activating the fault (controlling it), plus the cost of observing the fault (propagating it). • Why do this? • figure out what’s hard to test, and redesign the circuit. a-sa0 VLSI Design II

32. Summary • These costs are heuristics • the magnitudes have little physical meaning — # of inputs • they are meant to be easily-calculated indicators of: • which gate to select from the D-frontier • which gate input to select for backtracing or J-frontiering • they can’t be more difficult to calculate than actually selecting the wrong gate or gate input. • thus the logic function is not considered • But, • they are important for trimming the search space of the ATG algorithms VLSI Design II