1 / 3

Managing Advanced Node Variability with In-Design and Sign-off DFM

Managing Advanced Node Variability with In-Design and Sign-off DFM. Signoff Seminar November 2013 Philippe Hurat - Product Management Director – DFM – DSG. DFM is About Yield. Cadence Solution. Manufacturing issue. Impact on design.

aram
Download Presentation

Managing Advanced Node Variability with In-Design and Sign-off DFM

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Managing Advanced Node Variability with In-Design and Sign-off DFM Signoff Seminar November 2013 Philippe Hurat - Product Management Director – DFM – DSG

  2. DFM is About Yield Cadence Solution Manufacturing issue Impact on design Partner with foundries to qualify LPA and reduce runtime impact Trusted partner for DFM services Integrate automated fixing in design platform Mandatory Litho checks Increased runtimes (DPT) More hotspots to fix More DFM optimization required (via, notches, cut-masks, …) Litho(LPA) WELL DRC clean is NOT sufficient! what you draw is not what gets manufactured Increased Variations across entire stack 3D devices are sensitive to CMP IP integration issues Impact on interconnect parasitics Signoff and in-design CMP Hotspot detection and fixing guidelines Front End of Line Modeling Block-based analysis CMP-aware parasitic extraction CMP(CCP) Planarity and Thickness problems result in yield loss Erosion Dishing Total Copper Loss LDE analysis integrated in Virtuoso with fixing guidelines 20/16FF Std cell variability and context optimization for std cell characterization Context-aware critical path analysis Increased custom post-layout iterations and over design Increased margins and timing closure due to variability caused by LDE Electrical Variability (LEA, LDE) More and stronger Layout Dependent Effects (LDE) Impact device performance

  3. Cadence In-Design and Sign-Off DFM Solutions Encounter Signoff Virtuoso • Fast Litho (DRC+) hotspot prevention, detection, automated fixing & optimization • Standalone Litho sign-off • Litho hotspot detection, fixing & optimization Litho(LPA) 3- Foundry-certified DFM services: An alternative to meet mandatory DFM requirements By Rudy Mason – Cadence VCAD Services • DFM Services for TSMC customers: Litho and CMP • CMP hotspot detection and fixing guidelines • CMP-aware parasitic extraction • CMP hotspot detection & fixing guidelines • CMP Block-based analysis CMP(CCP) • Standalone CMP sign-off 2 - Macro Modeling based Layout Dependent Effect aware Design Flow By Pei YaoGLOBAL FOUNDRIES 1- Placement Dependent Variability Assessment of Standard Cell Libraries By C. Riccobene LSI Logic • Impact of LDE included in timing libraries • Variability-Aware Timing Analysis Electrical Variability (LEA, LDE) • LDE variability hotspots detection

More Related