Clockless Logic

1. Clockless Logic System-Level Specification and Synthesis Ack: Tiberiu Chelcea

2. passive port active port O1 O2 req ack Asynchronous Communication Protocols: Control Communication protocol: 4-phase handshake • O1 initiates communication • O2 completes communication Communication channel: req: operation start ack: operation done A Active phase Return-to-zero (RTZ) phase

3. O1 O2 Asynchronous Communication Protocols: Data A Channel parameters: • Data Encoding: bundled-data • Communication channel: 2 control wires + bundle of data wires • Data Flow Direction: • Push channel: data flows with the request • Pull channel: data flows with the acknowledge • Data Validity: broad, early, late • Broad: data valid for the entire handshake • Early: data valid during active phase of handshake • Late: data valid during return-to-zero phase of handshake • Data Item Type: byte, word, bool … • Data Width: # data wires to encode data item … The CH language needs to model all these parameters

4. O1 Obj Obj Interleaving of Two Communication Protocols Interleaving = combining behaviors on 2+ channels • Example #1: handshake on B enclosed within handshake on A • Example #2: handshake on B sequenced after handshake on A Different interleavings: provide different tradeoffs • Speed: latency/throughput • Area • Power … The CH language needs to model various interleavings B A

5. Balsa Language: High-Level Modeling • High-level asynchonous description language • Based on CSP • Block-structured, algorithmic • Each Balsa module communicates through handshaking with the environment Simple Example: One place Buffer procedure Buf1 (input i: byte; output o: byte) is local variable x : byte begin loop begin i -> x; o <- x end end

6. Balsa HDL Handshake Circuit procedure Buf1 ( input i: byte; output o: byte) is local variable x : byte begin loop begin i -> x; o <- x end end Start # syntax-directed translation ; unoptimized O I X Handshake Circuits: Intermediate Representation • Intermediate representation of Balsa/Tangram compilation • Handshake circuit = netlist of handshake components, connected by channels, corresponding to a Balsa program • Handshake component = primitive asynchronous component communicating only through handshaking

7. # ; Handshake Circuits • Intermediate representation of Balsa/Tangram compilation • Handshake circuit = netlist of handshake components, connected by channels, corresponding to a Balsa program • Handshake component = primitive asynchronous component communicating only through handshaking Start loop begin end i x -> ; o <- x O I X

8. # ; X Handshake Circuits • Intermediate representation of Balsa/Tangram compilation • Handshake circuit = netlist of handshake components, connected by channels, corresponding to a Balsa program • Handshake component = primitive asynchronous component communicating only through handshaking Start loop begin end i x -> ; o <- x O I X

9. # ; Handshake Circuits • Intermediate representation of Balsa/Tangram compilation • Handshake circuit = netlist of handshake components, connected by channels, corresponding to a Balsa program • Handshake component = primitive asynchronous component communicating only through handshaking Start loop begin end i x -> ; o <- x O I X

10. Large-Scale Asynchronous Systems: Overview small microprocessor core