Clockless Logic

1. Clockless Logic Prof. Montek Singh Feb. 27, 2003

2. Unclocked “Burst-Mode” State Machine Synthesis Acknowledgment Steven Nowick et al. (Columbia Univ.)

3. “Burst-Mode” Controllers Synthesis style for individual asynchronous FSM’s: • Mealy-type • allows: • multiple-input changes • concurrent behavior • target technology: normal synchronous cell libraries • optimization algorithms: comprehensive set • Brief History:... • Based on informal approach at HP Labs: • Davis, Coates, Stevens [1986-, and earlier] • Formalized and constrained at Stanford: Nowick/Dill [91] • Nowick/Dill first to develop a correct synthesis method

4. Burst-Mode: Implementation Style “Huffman Machine”: async machine, no explicit latches inputs outputs A X B Y Hazard-Free Combinational Network C Z state (several bits)

5. Burst-Mode: Implementation Style Burst-Mode Behavior: inputs in a user-specified ’input burst’ arrive, in any order (glitch-free) inputs outputs A+ X B Y Hazard-Free Combinational Network C Z state (several bits)

6. Burst-Mode: Implementation Style Burst-Mode Behavior: inputs in a user-specified ‘input burst’ arrive, in any order inputs outputs A+ X B Y Hazard-Free Combinational Network C- Z state (several bits)

7. Burst-Mode: Implementation Style Burst-Mode Behavior: once ‘input burst’is complete, machine generates a (glitch-free) ‘output burst’ … inputs outputs A X B Y- Hazard-Free Combinational Network C Z+ state output burst input burst (several bits)

8. Burst-Mode: Implementation Style … and (sometimes!) a concurrent (and glitch-free)state changeto a new state…. inputs outputs A X B Y Hazard-Free Combinational Network C Z state output burst input burst (several bits) state change

9. 1 2 Burst-Mode Specifications current state A+ C-/ Y- Z+ How to specify “burst-mode” behavior?: input burst/ output burst next state inputs outputs A X B Y Hazard-Free Combinational Network C Z state output burst input burst (several bits)

10. 0 1 2 3 4 5 Burst-Mode Specifications Initial Values: ABC = 000 YZ = 01 Example: Burst-Mode (BM) Specification: A+ C+/ Z- - Inputs in specified “input burst” can arrive in any order and at any time A+ B+/ Y+ Z- - After all inputs arrive, generate “output burst” C-/ Z+ B- C+/ Z+ Note: -input bursts: must be non-empty(at least 1 input per burst) -output bursts: may be empty (0 or more outputs per burst) C+/ Y+ C-/ -- A-/ Y-

11. Burst-Mode Specifications “Burst-Mode” (BM) Specs: 2 Basic Requirements • requirements introduced by Nowick/Dill [ICCD’91,ICCAD’91] • … guarantee hazard-free synthesis! 1. “maximal set property”: in each specification state, no input burst can be a subset of any other input burst 2. “unique entry point”:each specification state must be entered at a ‘single point’

12. 0 0 1 1 2 2 Burst-Mode Specifications 1. “maximal set property”: in each specification state, no input burst can be a subset of another input burst A+/ Y+ Z- A+ C+/ Z- A+ C+/ Z- A+ B+/ Y+ Z- legal illegal:{A+}  {A+C+} …ambiguous:what to do when only input A+ arrives?: - wait for C+? or output Y+ Z-??

13. 0 0 1 1 2 2 Burst-Mode Specifications 2. “unique entry point”: each specification state must be entered at a ‘single point’ (guarantees hazard-free synthesis) A+/ Z+ A+/ Z+ C+/ Y+ C+/ Y+ B+/ Y+ B+/ Y+ D+/ Z+ D+/ Z+ Entering State 4: - from State 1: ABCD=1100 (YZ=11) - from State 2: ABCD=0011 (YZ=11) 4 4 5 illegal:2 different input/output values when entering state 4 legal: solution=split state 4

14. 0 1 2 3 5 Burst-Mode Specifications State 0: Initial Values ABC = 000 YZ = 01 Another Example: 2. “unique entry point” (cont.): A+ C+/ Z- A+ B+/ Y+ Z- this is legal:state 4 -- entered with the same input/output values on both ‘incoming arcs’ C-/ Z+ B- C+/ Z+ Entering State 4: - from State 3:ABC =101 (YZ=11) - from State 2: ABC = 101 (YZ=11)… so, “unique entry point” property is satisfied. C+/ Y+ 4 C-/ -- A-/ Y-

15. 0 1 2 3 5 Burst-Mode Specifications State 0: Initial Values ABC = 000 YZ = 01 Final observation:Burst-Mode specs must indicateall “expected events” Missing input burst = “cannot occur” A+ C+/ Z- A+ B+/ Y+ Z- C-/ Z+ B- C+/ Z+ EXAMPLE: in State #0…- the specification indicates (implicitly) that input burst B+C+ cannot occur … since this event is not specified! C+/ Y+ 4 C-/ -- A-/ Y-

16. 5 6 4 3 2 0 1 Burst-Mode Specifications ok+ Rin*/ FRout+ ok-Rin*/ -- “Extended Burst-Mode” (XBM): [Yun/Dill ICCAD-93/95] FAin+ Rin*/ FRout- New Features: FAin-Rin+/ Aout+ <Cnd->Rin-/ Aout- 1. “directed don’t cares” (Rin*):allow concurrent inputs & outputs 2. “conditionals” (<Cnd>):allow “sampling” of level signals <Cnd+> Rin-/ Aout- FRout+ Rin+ FAin-/ Aout+ Handles glitchy inputs, mixed sync/async inputs, etc. Rin* FAin+/ FRout- (… not yet supported by MINIMALIST, expected in future releases)

17. One-Sided Timing Requirements #1. Fedback State Change:must not arrive at inputs until previous input burst has been fully processed … • add: 1-sided delay to feedback path • usually negligible delay: often no extra delay needed inputs outputs A X B Y Hazard-Free Combinational Network C Z state 1-sideddelay

18. One-Sided Timing Requirements (cont.) #2. Next Input Burst:must not arrive until machine has stabilizedfrom previous input+state change … • often satisfied: environment usually “slow enough” • if not: add small delays to outputs inputs outputs A X B Y Hazard-Free Combinational Network C Z state delay

19. One-Sided Timing Requirements (cont.) #2. Next Input Burst (cont.):must not arrive until entire machine has stabilized … “Generalized Fundamental Mode”: after each input burst arrives, a machine ‘hold-time requirement’ must be satisfied, before environment applies the next input burst

20. 1 2 3 4 Example : Burst-Mode Synthesis Burst-Mode Specification: AR+/BR+ BA+/BR- AR-/AA- BA-/AA+

21. 1 2 3 4 Example : Burst-Mode Synthesis Burst-Mode Specification: Burst-Mode Implementation: AR BA BR AR+/BR+ BA AR AA BA+/BR- BA AR-/AA- AR Y0 BA-/AA+