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Initial Proposal

The goal is to study the following performance parameters : Radiation hardness (Barrel: 1.2x10 15 neq /cm 2 for innermost layer. Endcap : 1.6x10 15 neq /cm 2 and 58 MRad .) Signal-to-noise ratio ( S/N) Timing resolution, sigma(T) Power consumption ( P)

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Initial Proposal

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  1. The goal is to study the following performance parameters : • Radiation hardness (Barrel: 1.2x1015neq/cm2for innermost layer. Endcap: 1.6x1015neq/cm2 and 58 MRad.) • Signal-to-noise ratio (S/N) • Timing resolution, sigma(T) • Power consumption (P) • Interplay between S/N, sigma(T), and P. • Spatial efficiency map • Pixel size • Readout architecture of signal transfer along the strip • Operational thresholds • Noise hit rate • We’ll need different submissions with MPW runs to assess basic properties andarchitectural issues. Some key aspects might be difficult to figure out with small size prototypes, although we could check noise and cross-talk susceptibility. • Note: “Organic growth” development would probably not have the architectural submission now. But we have a very aggressive schedule to meet. Initial Proposal Stage 1 Submission proposal for CMOS Strips

  2. To answer the question on signal size, NIEL radiation hardness and drift/diffusion ratio, it would be good to separate the “Signal” and “Amplifier” part. Of course, the HV/HR-CMOS technology is inherently monolithic. But we want to be able to study the different parts and their change with radiation separately. • Proposed test circuits: • “Sensor” diodes, 3x3 pixels. Tests: signal development, depletion/capacitance, irradiation. Variation: pixel size, fill factor. • Integrated 5x5 pixels with amplifiers. Tests: depletion, CCE, irradiation. Variation: pixel size, fill factor. • Front-end amplifier without the “sensor” part, but with I/O test pads. Tests: gain, irradiation, shaping (?), timewalk (?). “Basic” Submission Stage 1 Submission proposal for CMOS Strips

  3. Partitioning the available area into 3 sub-sections to investigate the effect of different pixel size compared with the minimal 37x100 um2 (See also slide 5). Part 1: parallel traces to the periphery. Tests the channel density, pixel size. Can use different timewalk design for different pixels. Can implement traces near pixels to inject external signals (noise susceptibility). “Architectural” Submission Stage 1 Submission proposal for CMOS Strips

  4. Part 2: 2 complete channels with correct total length implemented in a “snaked” geometry. The idea is to test that OR’ing pixels does not cause problems. “Architectural” Submission (2) • Chip periphery should be close to final : • Timing and location information. • Tuning of shaping/thresholds, changing power. • Readout to an FPGA or equivalent. Stage 1 Submission proposal for CMOS Strips

  5. We had email discussions after the proposal was circulated: • (Ivan) A possibility of one 37x800 um2pixel instead of 8 OR'ed pixels with size 37x100 um2. This needs to be studies in terms of noise/power trade off with the different input capacitance. • (Ivan) No need for a special preamp for sensor studies, since the gain is large with 1-stage amp. • (Francis) An amplifier with short shaping time as an additional option. • (Francis) A question on acceptable threshold. Might be difficult to figure out without making a sizable chip. Could possibly study noise susceptibility. • (Renato) Need to be more explicit in terms of submitting to >1 foundry initially, and to include CIS process. Follow-up Stage 1 Submission proposal for CMOS Strips

  6. Renato’s point is very valid. • Then we may want to have >= 2 “basic” submissions along with at >= 1 “architecture” submission. • Ivan pointed out a possibility of Europractice MPW run on April 28, on 20 Ohm-cm substrate. Cost < 4 kEuro for 4 mm2. • He could implement “basic” things by himself, along with deep P-well isolation of PMOS transistors. • Also a possibility of engineering run with variable high-resistivity substrates late 2014 or early 2015. • How do we proceed: • Need to agree on the number of submissions, and to select foundries. • For the “basic” submission, we may want to figure out the possible dates now. • The “architecture” run is expected to be more manpower intensive. May need to identify the designers in the next 2 months or so to have a chance to submit at the end of the year. Submissions Stage 1 Submission proposal for CMOS Strips

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