The First Integration Test of the ATLAS End-cap Muon Level 1 Trigger System

1. The First Integration Test of the ATLASEnd-cap Muon Level 1 Trigger System • Introduction • Overview of ATLAS End-cap Muon Level1 Trigger • TGC electronics (Level1 Trigger + TGC Readout) • Slice Test Setup • Test Results • Summary Chikara Fukunaga Tokyo Metropolitan University On behalf of the ATLAS TGC electronics group NSS2002 in Norfolk, Virginia, USA

2. Introduction • 3 main ASICs out of total 7 have been made with full specifications. • Stand-alone tests of ASICs have been finished. • An overall integrated test has been required with all these ASICs in one test bed →Slice test (SLT) system. • C++ based trigger simulation program has been needed and developed, and it could give the test patterns and answers to the SLT system. • Integration test started in Sept.,’01, all the components have been installed in Aug.,’02. NSS2002 in Norfolk, Virginia, USA

3. M2 M3 M1 Overview of ATLAS End-cap Muon Level1 Trigger NSS2002 in Norfolk, Virginia, USA

4. TGC electronics (Level1 Trigger + TGC Readout) On detector part Off detector part M3 M2 NSS2002 in Norfolk, Virginia, USA M1

5. Slice Test (SLT) Setup NSS2002 in Norfolk, Virginia, USA

6. Trigger (Hi-pT) Readout (SSW) SLT Components I– PS Board & ASICs NSS2002 in Norfolk, Virginia, USA

7. SLT Components II - Hi-pT board & ASIC G-link out To SL NSS2002 in Norfolk, Virginia, USA LVDS in From PS board

8. CPU FIFO SDRAM G-link in From SSW SLT Components III – Readout System Star Switch (SSW) LVDS in From PS board (SLB) NSS2002 in Norfolk, Virginia, USA Read Out Driver (ROD) G-link out To ROD

9. SLT Components IV – Software system • Integrated control software based on the ATLAS online SW framework • SLT requires initialization and module/ASIC configuration at beginning • Run control for run start/stop Run Control GUI & Status Window NSS2002 in Norfolk, Virginia, USA Configuration DataBase Editor Window

10. SLT Results I – Trigger Part Logic • Verification of Trigger Logic (Simulation vs. HW) The same trigger hit patterns used for the simulation were inputted to PPG (pulse Pattern generators), and compared outputs of the SLT system with one of the simulation: • Generated Trigger Hit patterns, and comparison with the simulation • 1 track (~20000) → No error found. • 2 tracks (~20000) → No error found. • ≥ 3 tracks (~15000) → No error found. NSS2002 in Norfolk, Virginia, USA

11. SLT Results II - Trigger Latency Latency Measurement = Actual Measurement (PS board, HiPT and SL) AND Cable length Estimation 1205ns (SLT) < 1250ns (RUL) NSS2002 in Norfolk, Virginia, USA

12. SLT Results III – Readout test • Since SSW has been delivered in this summer, full test of PS-board→SSW→ROD has not been done. • PS-board→PT4(SSW alternative)→ROD has been checked in 2001 with long run tests. • 400 clock counts (40MHz) can be used for SLB or SSW readout if Level 1 rate is 100KHz. SLB uses 218 counts. If TGC occupancy is 4%, SSW needs 160 counts. SSW will not be bottle neck. (TGC Occupancy ~ 1%) NSS2002 in Norfolk, Virginia, USA

13. SLT Results - ROD RODStructure • ROD (Read Out Buffer) has several problems. • 4 bytes access to internal bus takes 0.2ms. • SSW No hits = 4bytes • SSW Hits = 40bytes • If all 13 SSWs have no hits, 14ms, if all hits, 30ms. • One ROD with 13 SSWs can be done with 30~70KHz (< 100KHz). • We need design modification. NSS2002 in Norfolk, Virginia, USA

14. Summary NSS2002 in Norfolk, Virginia, USA