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Rad-Tolerant design of all-digital DLL

Ramon Chips. Rad-Tolerant design of all-digital DLL. Ramon Chips is named in memory of Col. Ilan Ramon, Israeli astronaut who died on board the Columbia space shuttle, 1/2/2003. Tuvia Liran [tuvia@ramon-chips.com ] Ran Ginosar [ran@ramon-chips.com ] Dov Alon [dov@ramon-chips.com ]

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Rad-Tolerant design of all-digital DLL

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  1. Ramon Chips Rad-Tolerant design of all-digital DLL Ramon Chips is named in memory of Col. Ilan Ramon, Israeli astronaut who died on board the Columbia space shuttle, 1/2/2003 Tuvia Liran [tuvia@ramon-chips.com ] Ran Ginosar [ran@ramon-chips.com ] Dov Alon [dov@ramon-chips.com ] Ramon-Chips Ltd., Israel

  2. Outline • Issues with analog DLL/PLL • All-digital DLL (ADDLL) architecture • Radiation hardening of ADDLL • Applications of ADDLL • Integration of ADDLL in SOC • Future developments

  3. Issues with analog PLL • Issues: • Sensitive to TID of analog • Might un-lock due to SET • Accumulate phase error due to SET • Might miss cycle due to SET • Sensitive to process, voltage, temperature

  4. All-digital DLL concept • Standard cell based logic • Operates at wide range of process, voltage & temperature • Timing is controlled by logic • Fast locking / immediate re-locking • Low jitter – typically <1% of CLKREF period

  5. DCDL operation Gross tuning of delay Fine tuning of delay

  6. DCDL response to control code

  7. Radiation hardening of ADDLL • Key radiation hazards: • TID • SEL • Phase error due to SE • Clock spike due to SET • Reset/re-configure due to SEU/SET • RH mitigation techniques • The use of RadSafeTM std. cells – immunity to TID & SEL • Use of SEP flip-flops mitigates SEU – immunity to change in control • Glitch filtering at each DCDL stage – mitigates SET spikes • Requirements for double sampling of reset – mitigates SET in reset/load

  8. Advantages of ADDLL • Voltage range –as logic core • Temperature range –as logic core • Lock time –limited # of cycles • Re-locking time –immediate • Standby power –zero • Dynamic power –very low • Bursts of clocks - enabled • Control of slave delay lines - enabled • Area –very small • Floor planning – anywhere in the chip / I/O strip • Immunity to Soft-Errors - Optional

  9. ADDLL in RadSafeTM library

  10. All-digital DLL cores • Three DLL cores for 3 frequency ranges • Locking guaranteed • 0.05 mm2/core • 8 mW/core @0.18u • Highly protected from radiation effects • Can be placed anywhere in the core • Powered by core supply lines

  11. ADDLL application – de-skewing

  12. ADDLL application – frequency multiplication

  13. ADDLL application – master-slave operation

  14. Other optional applications • Frequency multiplication by 8X/16X… • Frequency multiplication by non 2n • Duty cycle re-construction • Digitally monitoring of aging/PVT • Operation with bursts of clocks • Frequency hoping

  15. Record of integrating ADDLLs

  16. Example of ADDLL (commercial IP) Dig I/F SlaveDCDL Slave CTRL SYNC PHD DCDL CTRL 80µ 140µ • TSMC/0.13u process • 200-500MHz input clock • Area: 0.01mm2 • Power: 2mW @1.2V • Located inside I/O ring • DDR2 application

  17. Summary • ADDLL provides significant advantages over analog PLL/DLLs • RH ADDLL overcomes the sensitivities of analog PLLs/DLLs • ADDLL can be used for clock de-skewing and multiplication, and other applications • RadSafeTM ADDLL is mature and proven

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