Chapter 4 Introduction to Computer Organization

1. Chapter 4 Introduction to Computer Organization

2. 4.1 Basic Computer Organization Bus (Refer to Figure 4.1) Address bus Data bus Control bus I/O bus (local bus)

3. Figure 4.1 Generic computer organization

4. Instruction Cycles • Instruction cycles • Fetch • Execute • System clock (Refer to Figure 4.2) • I/O • Isolated I/O • Memory mapped I/O

5. Figure 4.2 Timing for memory read and memory write

6. 4.2 CPU Organization • Figure 4.3 • Register section • General purpose registers • Special purpose registers • Program counter • Instruction registers, etc • Arithmetic/Logic unit(ALU) • Control Unit

7. Figure 4.3 CPU internal organization

8. 4.3 Memory Subsystem Organization and Interfacing • Types of Memory • ROM • Masked ROM • PROM(Programmable ROM) • EPROM(Erasable PROM) • EEPROM(Electrically Erasable PROM) • Flash EEPROM • RAM • Static RAM(SRAM) • Dynamic RAM(DRAM)

9. Internal Chip Organization • Linear organization (Figure 4.4) • Two-dimension organization (Figure 4.5)

10. Figure 4.4 Linear organization of an 8X2 ROM chip

11. Figure 4.5 Two-dimensional organization of an 8X2 ROM chip

12. Memory subsystem configuration • Some methods for combining memory chips to form a memory subsystem • Expansion of Data bits (Figure 4.6) • Interleaving (Figure 4.7) • High-order interleaving • Low-order interleaving • Using CE signal(Figure 4.8)

13. Figure 4.6 An 8 x 4 memorysubsystem constructed from two 8 x 2 ROM chips

14. Figure 4.7 (a) A 16 x 2 memory subsystem constructed two 8 x 2 ROM chips with high-order interleaving

15. Figure 4.7 (b) A 16 x 2 memory subsystem constructed two 8 x 2 ROM chips with low-order interleaving

16. Figure 4.8 An 8 x 4 memory subsystem constructed two 8 x 2 ROM chips with control signals

17. Historical perspective • Von Neumann architectures • Harvard architectures

18. Multibyte data organization • Table 3.1 • Big endian • Little endian • Alignment of multibyte words

19. Beyond the basics • Cache memory • Virtual memory

20. 4.4 I/O Subsystem Organization and Interfacing • Enable logic

21. Figure 4.9 An input device: (a) with its interface and (b) the enable logic for the tri-state buffers Its address is 11110000

22. Figure 4.10 An output device: (a) with its interface and (b) the enable logic for the tri-state buffers Its address is 11110000

23. Figure 4.11 A bi-directional input/output device with its interface and the enable logic

24. Interrupts and DMA?

25. 4.5 A Relatively Simple Computer • Figure 4.12 • Address bus: 16 bit • Data bus: 8bit • Control bus: 2bit(READ, WRITE) • ROM: 0 to 8K-1 • RAM: 8K to 16K-1 • I/O port address: 8000H

26. Figure 4.12 A relatively simple computer: CPU details only

27. Figure 4.13 A relatively simple computer: memory subsystem details

28. Figure 4.14 A relatively simple computer: Final design

29. 4.6 Real World Example: An 8085-base Computer • ALE signal: Address Latch Enable • 1: during the 1st clock of memory or I/O access • 0: for the duration of the access. • Demutiplexing

30. Figure 4.15 Demultiplexing the AD pins of the 8085 microprocessor

31. Figure 4.16 A minimal 8085-based computer system