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Ladder prototype tests (very preliminary). Infrastructure test board (ITB) with 10 sensors chained together Test plan Setup status Present issues Initial test results Summary. IPHC-LBNL Phone meeting 17 May 2010. Test plan. Debug the system (ITB, MTB, RDO, firmware, and software)
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Ladder prototype tests (very preliminary) Infrastructure test board (ITB) with 10 sensors chained together Test plan Setup status Present issues Initial test results Summary IPHC-LBNL Phone meeting 17 May 2010
Test plan • Debug the system (ITB, MTB, RDO, firmware, and software) • Compare probe test results with sensor performance on the ITB • Each chip tested individually • Individual characterization of sensor performance (one sensor running) • Scan of discriminator thresholds • Analog 55Fe calibrations • Sensor characterization on ITB – individual sensor characterization when all sensors are correctly configured and running • Sensor characterization on ITB as a function of different bias conditions • Additional resistance in power distribution • Different bias voltages • Data acquisition for all sensors at the same time
Setup status • Hardware is ready (ITB required minor patches) • E.g. missing MK_CLKD connection has been replaced with last column maker from Sensor 1 (first in chain) available at Tst2Pad • Full hardware setup: ITB, MTB, RDO, long cables. • Firmware is ready for the initial set of tests • Tuning IODELAY for all signal paths • Readout of one sensor at a time (selected with a parameter set at the acquisition time) • Software is ready (some tweaking as we go along) • Scripted procedures for data acquisition and data analysis
Present issues • JTAG programming for all sensors at once (BIAS_DAC, RDO, CTRL, LINEPAT …) is unreliable - it is necessary to repeat it • Programming of just a few sensors at once works well • We can program the whole chain with one JTAG sequence, as long as the BIAS_DAC is the last one in that sequence • Sync issue • One chip doesn’t synchronize to the same clock as the rest • Synchronizes well when power consumption on the ITB is reduced
Initial test results • Probe test results (not optimal settings) vs. • ITB test - one sensor at a time, other sensors set up but waiting for CMOS CLK vs. • ITB test - data acquisition for each sensor individually: other sensors are configured with 0 in DAC BIAS and CMOS CLK • The exception is chip 0 which generates the sync marker - the configuration is: LVDSTX and LVDS set, other DAC biases are 0s. • Power consumption @5.2 V ~ 1.6 A (measured at the power supply)
(chip C1) Probe tests ITB ITB (1 sensor) 40-column pattern attributed to problems with 1-clock marker mis-synchronization
Summary • Full hardware setup • ITB, MTB, RDO, long cables • Hardware, firmware, software – already compatible with most of the test plan • Multidrop clock working • JTAG daisy chain working (with caveats) • Test results feed back to our probe test setup • There are issues to be addressed • ITB tests are beginning • Full test report will be available hopefully soon
Ladder power consumption • All chips programmed • VDD 0.65 A => chip start => 0.71 A • VDA 0.73 A => chip start => 1.07 A • Power for MTB & ITB (@ 5.2V) • After power ON => 1.36 A • After JTAG programming => 2.44 A • After chip start => 2.84 A
Sync issues sensor 1 and 2 are on, the rest has CMOS clock and BIAS dac set: sensor 1 and 2 are on, the rest has CMOS clock and BIAS dac set: all sensors are ON: all sensors are ON: sensor 1 and 2 are on, the rest has CMOS clock and BIAS set to 0: sensor 1 and 2 are on, the rest has CMOS clock and BIAS set to 0:
(chip D9) Probe tests ITB ITB (1 sensors)