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Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique

2. Presentation Outline. Low Power Design in DSMConcept of sleep transistorsPrevious workSizing the sleep transistorBin-Packing techniqueSet-Partitioning techniqueConclusion and extended work done. 3. Why Low Power Design ?. Growing market of mobile and handheld electronic systems.Difficulty

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Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique

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    1. 1 Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique Mohab Anis, Shawki Areibi *, Mohamed Mahmoud and Mohamed Elmasry VLSI Research Group, University of Waterloo, Canada * School of Engineering, University of Guelph, Canada

    2. 2 Presentation Outline Low Power Design in DSM Concept of sleep transistors Previous work Sizing the sleep transistor Bin-Packing technique Set-Partitioning technique Conclusion and extended work done

    3. 3 Why Low Power Design ? Growing market of mobile and handheld electronic systems. Difficulty in providing adequate cooling. Fans create noise and add to cost. Heat dissipation impacts packaging technology and cost Increasing standby time of portable devices. In DSM regimes, leakage power has become as big a problem as dynamic power

    4. 4 Concept of sleep transistors

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