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COPING WITH INTERCONNECT

COPING WITH INTERCONNECT. Impact of Interconnect Parasitics. Nature of Interconnect. INTERCONNECT. Capacitance: The Parallel Plate Model. Typical Wiring Capacitance Values. Fringing Capacitance. Fringing Capacitance: Values. How to counter Clock Skew?. Interwire Capacitance.

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COPING WITH INTERCONNECT

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  1. COPING WITH INTERCONNECT

  2. Impact of Interconnect Parasitics

  3. Nature of Interconnect

  4. INTERCONNECT

  5. Capacitance: The Parallel Plate Model

  6. Typical Wiring Capacitance Values

  7. Fringing Capacitance

  8. Fringing Capacitance: Values

  9. How to counter Clock Skew?

  10. Interwire Capacitance

  11. Interwire Capacitance

  12. Impact of Interwire Capacitance

  13. Capacitance Crosstalk

  14. How to Battle Capacitive Crosstalk

  15. Driving Large Capacitances

  16. Using Cascaded Buffers

  17. tp in function of u and x

  18. Impact of Cascading Buffers

  19. Output Driver Design

  20. How to Design Large Transistors

  21. Bonding Pad Design Bonding Pad GND 100 mm Out VDD Out In GND

  22. Reducing the swing • Reducing the swing potentially yields linear reduction in delay • Also results in reduction in power dissipation • Requires use of “sense amplifier” to restore signal level

  23. INTERCONNECT

  24. Wire Resistance

  25. Interconnect Resistance

  26. Dealing with Resistance

  27. Polycide Gate Mosfet

  28. Modern Interconnect

  29. RI Introduced Noise

  30. Power and Ground Distribution

  31. Electromigration (1)

  32. Electromigration (2)

  33. RC-Delay

  34. RC-Models

  35. Reducing RC-delay Repeater

  36. The Ellmore Delay

  37. Penfield-Rubinstein-Horowitz

  38. INTERCONNECT

  39. Inductive Effects in Integrated Circuits

  40. L di/dt

  41. L di/dt: Simulation

  42. Choosing the Right Pin

  43. Decoupling Capacitors

  44. Packaging

  45. Bonding Techniques

  46. Tape-Automated Bonding (TAB)

  47. Flip-Chip Bonding

  48. Package-to-Board Interconnect

  49. Package Types

  50. Package Parameters

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