1 / 73

Introduction to PCI System Architecture

Introduction to PCI System Architecture. Introduction to PCI System. Direct-Connect Approach(VESA). Main memory. CPU. Local Bus. Cache. Memory Bus. Local Bus Device. Expansion Bridge. Local Bus Design Constraint : 1. Redesign is necessary for next generation processor.

aysha
Download Presentation

Introduction to PCI System Architecture

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Introduction to PCI System Architecture

  2. Introduction to PCI System

  3. Direct-Connect Approach(VESA) Main memory CPU Local Bus Cache Memory Bus Local Bus Device Expansion Bridge Local Bus Design Constraint: 1. Redesign is necessary for next generation processor. 2. Only one local device is permitted. 3. Design of local bus inter -face is difficult. 4. Transfer with one device is not permitted while the local bus is involved in a transfer with another device. Expansion Bus X-Bus Buffer Expansion Connectors X-Bus I/O Device I/O Device I/O Device

  4. Buffered Approach(VESA) CPU Local Bus Cache Memory Bus Expansion Bridge Bus Buffer Buffered Local Bus Expansion Bus X-Bus Buffer I/O Device I/O Device I/O Device X-Bus A maximum of three local bus devices can be placed on the buffered local bus. I/O Device I/O Device I/O Device

  5. Workstation Approach(PCI) Video Memory Main Memory CPU Memory Bus CPU Local Bus Host/PCI Cache/Bridge AudioPeripheral Motion Video Peripheral PCI Bus Expansion Bus Bridge Graphics Adapter SCSI Host Bus Adapter LAN Adapter LAN Video Frame Buffer Disk SCSI BUS Expansion Bus Tape Bus Master Memory Slave I/O Slave CD ROM

  6. Transfer Rate Comparison: Bus Bus Frequency Transfer Transfer Rate ISA 8.33 MHz 2 byte / 2 clock 8.33 MB/s EISA 8.33 MHz 4 byte / 1 clock 33 MB/s ( Burst Mode) VESA 33 MHz 4 byte / 1 clock 132 MB/s ( Read, Burst ) 4 byte / 2 clock 66 MB/s ( Write, Burst ) PCI 33 MHz 4 byte / 1 clock 132 MB/s 8 byte / 1 clock 264 MB/s 66 MHz 4 byte / 1 clock 264 MB/s 8 byte / 1 clock 528 MB/s ( Burst Mode )

  7. PCI: Peripheral Component Interconnect • Major PCI Revision 2.1 Features •  Processor Independence •  Support for up to 256 PCI functions per PCI bus •  Low power consumption ( Draw as little current as possible ) • Burst used for all read and write transfers •  Supports 66 MHz operation, 64bit bus width •  Fast access ( 60ns at bus speed 33 MHz ) •  Concurrent bus operation •  Bus master support •  Hidden bus arbitration •  Low pin count ( Initiator:49pins, Target:47 pins ) •  Transaction integrity check( Parity check) •  Three address spaces ( Memory, I/O, Configuration ) •  Auto configuration( Configuration register ) •  Software Transparency

  8. PCI-Compliant Device Signals For Slave only For Master only Required Signals Optional Signals AD[31:00] AD[63:32] Address/Data and Command 64-bit Extension C/BE[3:0]# C/BE[7:4]# PCI COMPLIANT DEVICE PAR PAR64 REQ64# FRAM# ACK64# TRDY# LOCK# Atomic Access Interface Control IRDY# INTA# STOP# INTB# DEVSEL# Interrupt Request INTC# IDSEL INTD# Error Reporting PERR# CLKRUN# Clock Control SERR# SBO# Snoop Result REQ# SDON Arbitration GNT# TDI TDO CLK TCK JTAG System RST# TMS TRST#

  9. PCI Bus Arbitration

  10. Initiator/ Target • Initiator ( Master ): The device that initiates a transfer • Target ( Slave ): The device that currently addressed by the initiator for the purpose of performing a data transfer PCI Arbiter GNT0# GNT1# GNT2# GNT3# REQ0# REQ1# REQ2# REQ3# PCI Device PCI Device PCI Device PCI Device MASTER Address, Command/ Data, Byte Enables/ Parity PCI Device Bridge DRAM SLAVE SLAVE SLAVE

  11. Master X Master Y PCI Bus Arbitration Algorithm First Group Master A Second Group Master B Master Z A B X A B Y A B Z A B X • Fairness ( fixed, rotational ) • Bus Parking( on specified master, on last master that acquired the bus ) • Hidden Bus Arbitration( REQ#, GNT#) • LT ( Latency Timer ): The minimum amount of time that the bus master is • permitted to retain ownership of the bus

  12. Example of PCI Bus Arbitration Between Two Masters ( Master B has higher priority than Master A) 1 2 3 4 5 6 7 8 9 10 11 12 CLK REQA# ( Master A -> Arbiter ) REQB# ( Master B -> Arbiter ) GNTA# ( Arbiter -> Master A ) GNTB# ( Arbiter -> Master B ) LT not expired FRAME# ( Master -> Target ) IRDY# ( Master -> Target ) TRDY# ( Target -> Master ) AD ADDRESS ADDRESS ADDRESS DATA DATA DATA DATA DATA ( Master <-> Target ) A B A

  13. Arbitration for Fast Back-To-Back Accesses 1 2 3 4 5 6 7 8 CLK REQ#- GNT# FRAME# AD ADDRESS DATA ADDRESS DATA IRDY# TRDY# DEVSEL#

  14. Delayed Transaction • Delayed Transaction Request Phase: Target latches the request and issues retry Transaction completes on the target bus Completion Phase: Target cannot respond within 16 clocks: MTXC Master 1. Address, Command, Byte Enables latched by PIIX4 2. Retry issued to MTXC ( Request Phase ) PIIX4 Target 3. Requested data fetched in buffer ( Completion Phase ) 4. Master Retries the transaction with the same address, command, data ISA Device OR no Retry within 215 clocks Discard the data

  15. Commands That can Use Delayed Transactions • Interrupt Acknowledge • I/O Read • I/O Write • Memory Read • Memory Read Line • Memory Read Multiple • Configuration Read • Configuration Write

  16. The PCI Commands

  17. PCI Command Types C/BE#[3:0] is used toindicate the command or transaction type during the address phase C/BE[3::0]# Command Type 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate

  18. PCI Interrupt Acknowledge Transaction 1 2 3 4 5 CLK FRAME # ( Host Bridge -> INT Controller ) AD Stable Pattern VECTOR ( Host Bridge < -> INT Controller ) C/BE # Byte Enables INT ACK CMD ( Host Bridge -> INT Controller ) IRDY # TRDY # DEVSEL # ( INT Controller-> Host Bridge ) GNT #

  19. Message Code Message Type ( on AD[15:0] 0000h Shut Down 0001h Halt 0002h x86-specific message 0003h-ffffh Reserved The Special Cycle Transaction( Halt / Shut Down) Terminated with Master Abort 1 2 3 4 5 6 7 8 CLK • For an initiator to • broad- cast a message • to one or more targets. • Message type • on AD[15:0] • Message-dependent • data field on AD[31:16] • Byte Enable on • C/BE#[3:0] FRAME# AD[31:0] Stable Pattern Message C/BE#[3:0] Special Cmd Byte Enables IRDY# TRDY# DEVSEL# GNT# 7 clocks

  20. The Read and Write Transfers

  21. Read Transaction ( 33.33 Mb/s ) CLK 1 2 3 4 5 6 7 8 9 FRAME# Wait state for bus ownership AD ADDRESS DATA-1 DATA-2 DATA-3 C/BE# BUS CMD BYTE ENABLES BYTE ENABLES BYTE ENABLES IRDY# One more clock before initiator ready to receive data Avoid bus contention TRDY# Some time is needed for fetching data DEVSEL# DATA PHASE DATA PHASE DATA PHASE ADDRESS PHASE

  22. Optimized Read Transaction ( 132 Mb/s) 1 2 3 4 5 6 7 8 Burst Transfer: 1. If target memory is cacheable. 2. If target memory is prefetchable CLK FRAME# AD Address Data1 Data2 Data3 C/BE# Byte Enables Byte Enables BUS CMD Byte Enables IRDY# TRDY# DEVSEL# GNT#

  23. Write Transaction ( 44.44 Mb/s ) CLK 1 2 3 4 5 6 7 8 9 FRAME# AD ADDRESS DATA-1 DATA-2 DATA-3 C/BE# BUS CMD Byte EN Byte EN BYTE ENABLES IRDY# TRDY# DEVSEL#

  24. Optimized Write Transaction ( 132 Mb/s) 1 2 3 4 5 6 7 8 CLK FRAME# AD Address Data1 Data2 Data3 C/BE# Byte Enables Byte Enables Byte Enables BUS CMD IRDY# TRDY# DEVSEL# GNT#

  25. Addressing • Addressing Sequence During Memory Burst  Linear ( or Sequential ) address mode  Cache Line wrap mode AD1 AD0 Addressing Sequence 0 0 Linear 0 1 Reserved 1 0 Cacheline wrap 1 1 Reserved • PCI I/O Addressing  AD[31:2] : Target DW of I/O space  AD[1:0] : The Least-significant byte within the DW that the initiator wishes to transfer with ( 00 = byte 0, 01 = byte 1 )

  26. 64 bit PCI Extension • REQ64#, ACK64#, PAR64, • AD[64::32], C/BE[7::4]

  27. 64-bit Read Request with 64-bit Transfer CLK 1 2 3 4 5 6 7 8 9 FRAME# REQ64# AD[31::00] ADDRESS DATA-1 DATA-3 DATA-5 AD[63::32] DATA-2 DATA-4 DATA-6 C/BE[3::0]# BE# ‘s BUS CMD C/BE[7::4]# BE# ‘s IRDY# TRDY# DEVSEL# ACK64#

  28. 64-bit Write Request with 32-bit Transfer CLK 1 2 3 4 5 6 7 8 9 FRAME# REQ64# AD[31::00] ADDRESS DATA-1 DATA-2 DATA-3 AD[63::32] DATA-2 C/BE[3::0]# BUS CMD BE# ‘s-1 BE# ‘s-2 BE# ‘s-3 C/BE[7::4]# BE# ‘s-2 IRDY# TRDY# DEVSEL# ACK64#

  29. 64-bit Dual Address Read Cycle CLK 1 2 3 4 5 6 7 8 FRAME# AD[31::00] LO-ADDR HI-ADDR DATA-1 DATA-3 C/BE[3::0]# DUAL AD BUS CMD BE# [3::0] AD[63::32] HI-ADDR DATA-2 DATA-4 C/BE[7::4]# BUS CMD BE# [7::4] IRDY# TRDY# DEVSEL# REQ64# ACK64#

  30. Premature Transaction Termination

  31. Master Initiated Termination • Reasons • Transaction completed normally ( Not premature transaction termination ) • Initiator been preempted ( GNT# removed )  Preemption during timeslice by another bus master  Timeslice expiration followed by preemption • Master abort  No target respond to the address ( DEVSEL# not asserted)  No device resides at the address  Special cycle  Configuration accessing a non-existent target

  32. Preemption Example 1 2 3 4 5 6 7 CLK Preempted GNT# FRAME# Internal LT time out sensed IRDY# TRDY# Timer Expiration Example CLK Preempted GNT# FRAME# Time out sensed IRDY# TRDY#

  33. Example of Master-abort on Single-Data Phase Transaction 1 2 3 4 5 6 7 8 CLK FRAME# IRDY# TRDY# Fast Medium Slow Bridge DEVSEL# Master Abort : Target doesn’t claim transaction

  34. Target Initiated Termination( STOP# ) • Disconnect • Reasons • Target slow to complete a data phase which is neither the first nor the final data phase ( more than 8 PCI clocks ) • Targets don’t support burst mode • Memory target doesn’t understand address sequence • Transfer cross over target’s address boundary • Burst memory transfer crosses cache line boundary • Retry ( if the target cannot permit any data to be transferred ) • Reasons • Target very slow to complete first data phase ( Greater than 16 PCI clocks ) • Snoop hit on modified cache line • Resource busy • Memory target locked

  35. Target Abort ( if the target detects fatal error ) • Reasons • Broken Target • I/O addressing error • Address phase parity error • Master abort on other side of PCI-to-PCI bridge

  36. Type A Disconnect Type B Disconnect Know in advance that the next data transfer takes more than 8 PCI clock 1 2 3 4 1 2 3 4 CLK CLK FRAME# FRAME# IRDY# IRDY# TRDY# TRDY# STOP# STOP# DEVSEL# DEVSEL# Data Transfer Data Transfer TRDY# asserted, STOP# asserted, DEVSEL# asserted, IRDY# deasserted TRDY# asserted, STOP# asserted, DEVSEL# asserted, IRDY# asserted

  37. Type C Disconnect with IRDY# Asserted Type C Disconnect without IRDY# Asserted Current data transfer takes more than 8 PCI clock 1 2 3 4 1 2 3 4 CLK CLK FRAME# FRAME# IRDY# IRDY# TRDY# TRDY# STOP# STOP# DEVSEL# DEVSEL# TRDY# deasserted, STOP# asserted DEVSEL# asserted Data Transfer Data Transfer

  38. Retry Received With IRDY# Asserted Retry Received Without IRDY# Asserted 1 2 3 4 1 2 3 4 CLK CLK FRAME# FRAME# IRDY# IRDY# TRDY# TRDY# STOP# STOP# DEVSEL# DEVSEL# TRDY# deasserted, STOP# asserted DEVSEL# asserted No Data Transfer No Data Transfer Occurs in the first data phase

  39. Target Abort Example 1 2 3 4 CLK FRAME# • Master’s response to target abort: • Generates an interrupt to alert is related • device to check its status. • Generates SERR# IRDY# TRDY# STOP# DEVSEL# TRDY# deasserted, STOP# asserted DEVSEL# deasserted

  40. Shared Resource Acquisition

  41. Shared Resource Acquisition • LOCK#  Usage : Perform read/modify/write of a memory semaphore as an atomic series to avoid Synchronization Problem.  Solutions: Bus LOCK : Permissible but not preferred Resource LOCK: Preferred

  42. Starting an Exclusive Access ( Establishing LOCK#) 1 2 3 4 5 CLK FRAME# ( Master -> Target ) LOCK# ( Master -> Target ) AD ADDRESS DATA ( Master < -> Target ) IRDY# ( Master -> Target ) TRDY# ( Target -> Master ) DEVSEL# ( Target -> Master ) GNT# ( Arbiter -> Target ) • LOCK# Mechanism Availability: •  Do not assert REQ# if LOCK# is currently asserted. •  If FRAME# and LOCK# are deasserted, assert its REQ#. •  The master continue to monitor LOCK# while waiting for GNT#. • If LOCK# is sampled asserted, the master deasserted its REQ#. •  When the master samples bus idle ( FRAME# & IRDY# deasserted) • and LOCK# deasserted, it has acquisition of the bus and of the • LOCK#.

  43. Accessing a Locked Agent : Retry 1 2 3 4 5 CLK FRAME# (driven low by master holding lock) LOCK# ADDRESS DATA AD IRDY# TRDY# STOP# DEVSEL# Retry GNT#

  44. Continuing & Completing an Exclusive Access 1 2 3 4 5 CLK FRAME# Release LOCK# Continue ADDRESS DATA AD IRDY# TRDY# DEVSEL# GNT#

  45. Error Detection and Handling • When Parity Error occurs: • Configuration status register : DETECTED PARITY ERROR • Configuration command register: PARITY ERROR RESPONSE • Assert PERR# • Devices excluded from PERR# Requirement • Chipsets • Devices that don’t deal with OS/Application program or data

  46. Parity on Read Transaction 1 2 3 4 5 6 7 8 9 CLK FRAME# AD 1st Data 2nd Data Address 3rd Data C/BE# 1st Byte Enables 2nd Byte Enables 3rd Byte Enables BUS CMD PAR Add phase parity 1st Data parity 2nd Data parity 3rd Data Parity 3rd phase PERR# earliest latest PERR# 1st phase PERR# 2nd phase PERR# IRDY# TRDY# DEVSEL#

  47. Parity on Write Transaction 1 2 3 4 5 6 7 8 9 CLK FRAME# AD 1st Data 2nd Data Address 3rd Data C/BE# 1st Byte Enables 2nd Byte Enables BUS CMD 3rd Byte Enables PAR Add phase parity 1st Data parity 2nd Data parity 3rd Data Parity 3rd phase PERR# earliest latest PERR# 1st phase PERR# 2nd phase PERR# IRDY# TRDY# DEVSEL#

  48. Configuration Related Issues

  49. Configuration Address Space Format Byte Number 3 2 1 0 00 Double Word Number Configuration Header Space 15 16 Device Specific Configuration Registers 63

  50. Configuration Registers Type 0 Configuration Space Header 0 31 16 15 Required configuration registers Device ID Vendor ID 00h Command 04h Status Revision ID 08h Class Code Latency Timer Cache Line Size BIST 0Ch Header Type 10h Base Address Registers 24h 28h Cardbus CIS Pointer 2Ch Subsystem ID Subsystem Vendor ID Expansion ROM Base Address 30h 34h Reserved 38h Reserved 3Ch Max_Lat Min_Gnt Interrupt Pin Interrupt Line

More Related