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95-1 Under-Graduate Project Final Project Presentation

95-1 Under-Graduate Project Final Project Presentation. Speaker: 許名宏 陳柏偉 Advise: Prof. An-Yeu Wu Mentor: 陳彥良 Date: 2007/1/22. Outline. RTL structure RTL Coding Style SQNR Computation Deciding Bit Lengths New Decision Gate Level Synthesis Results Conclusion Reference.

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95-1 Under-Graduate Project Final Project Presentation

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  1. 95-1 Under-Graduate ProjectFinal Project Presentation Speaker: 許名宏 陳柏偉 Advise: Prof. An-Yeu Wu Mentor: 陳彥良 Date: 2007/1/22

  2. Outline • RTL structure • RTL Coding Style • SQNR Computation • Deciding Bit Lengths • New Decision • Gate Level • Synthesis Results • Conclusion • Reference

  3. RTL Structure

  4. RTL Coding Style (1/4) Since the judgment score is (Timing)^2 x Area, power is beyond our consideration, so we choose shift register to reduce area.

  5. RTL Coding Style (2/4) The procedure of “adding after MUX” can reduce the usage of ADDERs, and making the area smaller.

  6. RTL Coding Style (3/4) - Use counter to decide + or – - -A = ~A Just invert A. - Ignoring adding1,due to propagation delay (the last 2 bit should be cut after multiplier so we can ignore the adding 1)

  7. RTL Coding Style (4/4) • Each butterfly use different input & output bits (all at the same ratio), to reduce area • Use small module to pre-estimate area, e.g. each butterfly need ~8000 .

  8. SQNR Computation

  9. Deciding Bit Lengths The results match our matlab fixed-point simulation. Adding another bit to input and output does not improve SQNR as obvious as adding a bit to twiddle factor.

  10. New Decision – In=10 Out=16 W=9 - 011111111 +1 => 100000000 While we often encounter twiddle factor value 511(011111111), we add1 to 511, makes it become 512(10000000). - Critical path = 10 16 9 - Precision = 10 16 10 - Area In this way, adding extra MUXs does not slower the circuit. However, it remains the precision as we use 10 bits on twiddle, without changing critical path.

  11. Gate Level for In=10 Out=16 W=9 • - Gate level SQNR = ~53

  12. Synthesis Results We can roughly find out when timing gets smaller, area & dynamic power get bigger.

  13. Conclusion • Better coding style that efficiently reduce area : (1) shift register (2) adding after MUX (3) faster subtraction (4) different bits for each butterfly • Find out timing , lower power. When designing low power device this will be an important issue.

  14. Reference • [1] S. He and M. Torkelson. A new approach to pipeline FFT processor. Proceedings of IPPS’96, 1996

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