103-1 Under-Graduate Project FFT

1. 103-1 Under-Graduate ProjectFFT Speaker:林祐民(Yumin) Adviser: Prof. An-Yeu Wu Date: 2014/9/23

2. Access Lab Profile/Overview • Location: EE building II (Rm. 232, 14坪) • Manpower: • 6 Ph.D. students • 13 MS students • Equipment: • 3 Sun Blade 2000 Workstations • 2 Sun Ultra 60 Workstations • 24 PC and 6 Notebooks for students

3. 有關指導教授 • 99年度「中國電機工程學會傑出電機工程教授獎」 • 96年8月1日借調工研院系統晶片中心副主任 • 95年度台大共同教育委員會 - 「教學優良獎」 • 95年度第七屆旺宏金矽獎-半導體設計與應用大賽：「指導教授獎」(應用組、設計組) • 94年8月1日升等教授 • 94年度國科會「吳大猷先生紀念獎」（微電子學門唯一提名） • 94年度「國立臺灣大學傅斯年獎（肯定 SCI 學術期刊論文發表之學術貢獻）」 • 93年度「中國電機工程學會優秀青年電機工程師獎」 • 93年度「中國工程師學會工程論文獎」 • 93年度第四屆旺宏金矽獎-半導體設計與應用大賽：「最佳指導教授獎」 • 92年度「旺宏電子青年教授講座」 • 86、87、88、89年度國科會甲等研究獎勵共四次 • 88年度教育部「VLSI與系統設計」教育改進計畫佳作 (課程：可程式性信號處理器專題) • 國科會「微電子學門」計畫複審委員 • 教育部 SOC 聯盟「系統晶片設計實驗」總主持人 • 第 15 屆 VLSI/CAD Symposium 議程主席 • 我國 IA 旗鑑產品推行小組規格起草委員 • 經濟部技術處「業界開發產業技術計畫」審查委員 • 經濟部工業局「審核係屬科技事業暨產品或技術開發成功且具市場性意見書評估委員會」專案委員 • Associate Editor：IEEE Transactions on VLSI Systems • Associate Editor：EURASIP Journal on Applied Signal Processing • Technical Program Committee Member of Major IEEE International Conferences: ICIP, SiPS, AP-ASIC, ISCAS, ISPACS, ICME, APCCAS, and ASIC/SOC.

4. 92年度大專院校矽智產設計競賽：Soft IP 佳作/Hard IP 「優等」 第一屆全國SOC系統晶片設計比賽 軟硬體發展平台組 「優等獎 」 SoC晶片組 「優等獎」 94年度中國工程師學會全國大學部工程論文競賽 電資組「特優 」 94年度台灣積體電路設計學會「博士論文獎」 94 & 95學年度電子所年度「最佳碩士論文獎」 2010 IEEE VLSI-DAT 「最佳會議論文獎」 旺宏金矽獎-半導體設計與應用大賽： 第四屆「優等獎」及「新手獎」 第五屆設計組-設計組「最佳創意獎」 第七屆設計組-應用組「銅牌獎」、設計組「優勝」、設計組「銅牌獎」、設計組「最佳創意獎」 第八屆設計組「優勝獎」x2 第九屆設計組「金獎」、設計組「最佳創意獎」、設計組「銅獎」 2004,2005,2007,2008,2009,2010 國家晶片系統設計中心「優良晶片」設計 2007鳳凰盃IC設計競賽數位IC組「優等獎」 大學院校積體電路設計競賽： 94,95,96,98學年度研究所組標準單元設計 「佳作」 99 學年度研究所組標準單元設計 「特優」「佳作」 100 學年度研究所組標準單元設計 「優等」「佳作」 101 學年度研究所組標準單元設計 「特優」「優等」 指導學生獲獎

5. From 3C to ICS 3C Access IC Lab Focus Computer VLSI Access 3C lab. Content/ Consumer Communication & Networking Communication DSP ICS: Integrated Circuits and Systems

6. Project Topics for Undergraduate Members

7. Topics Basic Part • Fast Fourier Transform (FFT) Project - from algorithms to circuit implementation and analysis Research Part • 高效率信息擷取系統:壓縮感知技術 (Efficient Information Acquisition System via Compressive Sensing) • 具錯誤恢復機制之多核心系統設計 (Error-Resilient Multi-core System)

8. ICDesignandImplementation Idea Design

9. FFT- From Algorithm to Architecture&Chip >>fft(x); Algorithm Level DataFlow Fixed-Point Analysis Architecture Mapping Architecture Level HDL:Verilog Synthesis Layout Chip

10. Verilog test bench Cell-based Design Flow Focus!! Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Specification (FFT Algorithm) Verilog RTL Coding Tools Design Stage Functional simulation & Verification Matlab or C++ Spec. Modelling Verilog Design Text Editor Simulation NCverilog VCS Logic Synthesis Tech. file Synthesis Design Compiler (Mapping, Placing & Routing) Pyhsical Design & Implementation SoC Encounter IC Compiler Physical Layout sdc Chip

11. Verilog HDL • HDL – Hardware Description Language • Why use an HDL • Hardware is becoming very difficult to design directly • HDL is easier and cheaper to explore different design options • Reduce design time and cost • Goal • HDL has high-level programming language constructs and constructs to describe the connectivity of your circuit • Ability to mix different levels of abstraction freely • One language for all aspects of design, test, and verification

12. Project Goal • Architecture Design & Fixed-Point Analysis • Front-End Digital IC Design Flow Training • Behavioral Modeling: C or Matlab • Hardware Description Language: Verilog • Design Issue: • Application • UWB System • Biomedical Applications • Different Architectures of FFT • Pipelined FFT • Memory-based FFT • Speed 、Area and Power

13. Midterm: Fix-Point Analysis Algorithm Level Fixed-Point Analysis Architecture Level Optimal set: 2+6 = 8 Integer 2 bits Fractional 6 bits HDL:Verilog & Synthesis Chip

14. Final: Hardware Implementation Algorithm Level Fixed-Point Analysis Architecture Level HDL:Verilog & Synthesis Chip

15. FFT • 適合對象 • 對Digital IC Design有興趣的同學 • 條件 • Switch Logic Circuits, VLSI Design and Signal and System • 內容 • Skills for Research • Paper Reading • Presentation • Skills for Digital System Design • Digital IC Design Flow : Verilog Coding  Synthesis • Design Flow for DSP Architecture Mapping, Design, and Verification • Behavioral Modeling and Fixed-Point Analysis: C or Matlab

16. Schedule

17. Location & Time&Grading • Classroom Location: • EEII-229 • Lecture Time: • Tuesday 18:30 • Grading • Homework: 20% • Participation: 10% • 課程教學 • Mentor討論: 20% • 進度要求:10%,參與度:10% • Project Present: 50% (期中報告20% 期末報告30%) • Contact • 林祐民 -yumin@access.ee.ntu.edu.tw

18. Topics Basic Part • Fast Fourier Transform (FFT) Project - from algorithms to circuit implementation and analysis Research Part • 高效率信息擷取系統:壓縮感知技術 (Efficient Information Acquisition System via Compressive Sensing) • 具錯誤恢復機制之多核心系統設計 (Error-Resilient Multi-core System)

19. Age of Information Explosion • Demand of information is increased • Internet of things (IoT) & cognitive computing • Is the higher speed and larger scale system the only solution?

20. How Does Brain Work? [1]

21. Compressive Sensing [2][3] • Traditional digital data acquisition • Sample data with Nyquist rate • Compress data • Compressive sensing • Main idea: compression within sampling → solving sparse solution to underdetermined problem

22. Efficient Information Acquisition • Where is the black ball? • Progress of information acquisition Compressive Sensing Random Sample Sampling Theorem 2004 1985 1949

23. Measurement • From orthogonal basis sensing to non-orth. sensing X =(x0, x1, x2, x3,∙∙∙∙∙∙∙, xn) V0=(1, 0, 0, 1, ∙∙∙∙∙∙, 0) V1=(0, 1, 0, 0,∙∙∙∙∙∙, 0) ⁞ Vm=(0, 0, 1, 0, ∙∙∙∙∙∙, 1) Y = V∙X X =(x0, x1, x2, x3,∙∙∙∙∙∙∙, xn) V0=(1, 0, 0, 0, ∙∙∙∙∙∙, 0) =δ [k] V1=(0, 1, 0, 0,∙∙∙∙∙∙, 0) =δ [k-1] ⁞ Vn=(0, 0, 0, 0, ∙∙∙∙∙∙, 1) =δ [k-n] Y = V∙X CS y0 = x0+x3 y1 = x1 +x8 ⁞ ym = x2+xn y0=x0 y1=x1 ⁞ yn = xn Non-deterministic Polynomial-time Problem Full rank

24. Reconstruction Algorithms • Solve non-deterministic polynomial-time problem • Challenge • Possible but not practical • Hard to implement • Robustness & Speed

25. Project Goal • Measurement matrix construction • Information acquirement • Efficient reconstruction algorithm and VLSI design

26. Compressive Sensing • 適合對象: • 對前瞻信息獲得演算法有興趣的同學 • 未來想加入實驗室的同學 • 條件: • 一顆充滿熱情的心 • 內容: • 學習線性規劃最佳會求解 • 學習random sampling問題的求解 • 學習underdetermined問題的求解 • 熟悉Matlab基本應用

27. Location & Time&Grading • Classroom Location: • EEII-229 • Lecture Time: • Tuesday 19:30 (Flexible，2 Week) • Grading • Mentor討論:50% • Final Present: 50% • Contact • 林祐民 -yumin@access.ee.ntu.edu.tw

28. Topics Basic Part • Fast Fourier Transform (FFT) Project - from algorithms to circuit implementation and analysis Research Part • 高效率信息擷取系統:壓縮感知技術 (Efficient Information Acquisition System via Compressive Sensing) • 具錯誤恢復機制之多核心系統設計 (Error-Resilient Multi-core System)

29. Challenge of Reliable Green Computing Circuits and Systems

30. Why Error Resilient • Statistical Error Resiliency (2013, SIPS, Shanbhag) [2] • Robustness (1000x) Energy efficiency (3x-6x) • Logic level error resiliency (LLER): NMR, Cascaded NMR • Micro-architecture error resiliency (MLER): ERSA • System level error resiliency (SLER): ANT, Soft-NMR, SSNoC, LP 2011~ 2009~ NMR: N-modular redundancy ERSA: Error-resilient system architecture ANT: algorithmic noise tolerance SSNoC: stochastic sensor network-on-chip LP: likelihood processing [2]

31. Advantage of System Level Error Resilient • No worst-case protection but error resiliency (2013, ICASSP, Shanbhag) [2] • Stochastic applications • Energy efficient • Inherent resiliency to errors (2012, ERSA) [1] • Iterative computation • Probabilistic representation • Input from the real world • Cognitive resilience • Recognition, mining, and synthesis (RMS) applications, media processing, immersive computing[2] • Evaluation through BER, probability of detection, PSNR • Admit approximate error correct/compensation

32. Application: Stereo Matching • Use the disparity of two image to simulate human’s eyes and calculate the depth of the object • Disparity computation can be derived as a Markov random field problem • Highly using in robotics, TV game players and automobile electronics

33. Goal: Stereo Matching via ERSA • Use ERSA-based architecture to construct error-resilience stereo matching • Actual hardware error implementation • Error-resilience algorithm development Data output w/ hw error Data input Error correct

34. Application: LDPC Decoder Bit node • Decoding algorithm of LDPC • Iterative belief propagation • Soft-decision • The messages are the conditional probability that the received bit is a 1 or a 0 given the received vector • Inherent error tolerance • Probabilistic application • Iterative computation • Performance of LDPC codes under faulty iterative decoding Check node

35. Proposed Method • Error detection • Significant data reuse • The relation between inputs and outputs • The function in a bit node • Initialize the LLR (li) based on the received vector • Update the LLR • Decide output in the last iteration li + + mij . . . mji . . . error detect . . find max Bit node

36. Access CERES Project • 適合對象: • 對多核心系統、錯誤回復演算法設計有興趣的同學 • 未來想加入實驗室的同學 • 條件: • 一顆充滿熱情的心 • 內容: • 學習基本多核心系統運作原理 • 學習各層級錯誤容忍設計方法 • 以Matlab或C/C++模擬演算法效果

37. Location & Time&Grading • Classroom Location: • EEII-229 • Meeting Time: • Flexible，2 Week • Grading • Mentor討論:50% • Final Present: 50% • Contact • 李懷霆-wesli@access.ee.ntu.edu.tw • 李鼎元 -dan@access.ee.ntu.edu.tw