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RAL / UPPSALA Paul Seller I/O TSVs with T-Micro 3DIC with EMFT Munich

RAL / UPPSALA Paul Seller I/O TSVs with T-Micro 3DIC with EMFT Munich. I/O TSV with T-Micro. No Bond pads!. 4*80 test 4S ASIC. 4S. Hexitec ASIC with TSVs, wire-bonding on back working last year. Thinned to 120um. New ‘4S’ ASIC with small readout region.

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RAL / UPPSALA Paul Seller I/O TSVs with T-Micro 3DIC with EMFT Munich

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  1. RAL / UPPSALAPaul SellerI/O TSVs with T-Micro3DIC with EMFT Munich

  2. I/O TSV with T-Micro No Bond pads! 4*80 test 4S ASIC 4S Hexitec ASIC with TSVs, wire-bonding on back working last year. Thinned to 120um. • New ‘4S’ ASIC with small readout region. • Right: Test 80*4 pixel device with conventional bond pads (far right). Device tested and working. • Left: 80*70 ‘4S’ ASIC shows small non-pixel region on 4th side. Note no bond pads visible so can only test when TSVs are in place.

  3. I/O TSV with T-Micro • Plan: • T-Micro now processing 2 wafers. Ready August. • Mechanics and test system ready for wire bonding to standard Hexitec readout system.

  4. 3DIC EMFT

  5. 3DIC EMFT Processing steps nearly finished except final SLID bonding. See top of W vias (3*10um) through connect area.

  6. 3DIC EMFT Back of W vias (3*10um) through wafer. Back of vias filled after Al and copper electroplating. Ready now for Sn and SLID.

  7. 3DIC EMFT • Plan: • SLID Bonding happening this week. • Then checking and device segmentation. • Parts will be shipped to RAL for wire bonding and start of testing on electronic test system.

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