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Introduction to Verilog HDL

Introduction to Verilog HDL. Hardware Description Language (HDL). What is the need for Hardware Description Language? Basic idea is a programming language to describe hardware Model, Represent, And Simulate Digital Hardware Hardware Concurrency Edge Transitions Propagation Delays

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Introduction to Verilog HDL

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  1. Introduction to Verilog HDL

  2. Hardware Description Language (HDL) • What is the need for Hardware Description Language? • Basic idea is a programming language to describe hardware • Model, Represent, And Simulate Digital Hardware • Hardware Concurrency • Edge Transitions • Propagation Delays • Timing Checks • There are many different HDLs • Verilog HDL • VHDL • ABEL

  3. Comparison Between VHDL and Verilog VHDL • ADA-like verbose syntax. • Extensible types and simulation engine • Design is composed of entities each of which can have multiple architectures • Gate-level, dataflow, and behavioral modeling. Synthesizable subset. • Harder to learn and use. Verilog • C-like concise syntax • Built-in types and logic representations • Design is composed of modules which have just one implementation • Gate-level, dataflow, and behavioral modeling. Synthesizable subset. • Easy to learn and use, fast simulation.

  4. Module • The basic unit of description in the Verilog is the module. • A module describes the functionality of the design and states the input and output ports. • Basic syntax of a module: module module_name(port_list); Declarations: reg,wire,parameter, input,output,inout…. Statements: Initial , Always statement Module , Gate instantiation Continuous assignment endmodule

  5. Code Format • Verilog code is free format. • Spaces and new lines are served as separators. • It is case sensitive. • Language keywords use lowercase characters. • A comment designator start with // makes the rest of line comment. • The symbols /* … */ bracket the section of code which is in between as a comment.

  6. Lexical Conventions • Operators Logical operators: • &&  logical AND • ||  logical OR • !  logical NOT • Operands evaluated to ONE bit value: 0, 1 or x • Result is ONE bit value: 0, 1 or x A = 6; A && B  1 && 0  0 B = 0; A || !B  1 || 1  1 C = x; C || B  x || 0  x but C&&B=0

  7. Bitwise Operators: • &  bitwise AND • |  bitwise OR • ~  bitwise NOT • ^  bitwise XOR • ~^ or ^~  bitwise XNOR • Operation on bit by bit basis

  8. Reduction Operators: • &  AND • |  OR • ^  XOR • ~&  NAND • ~|  NOR • ~^ or ^~  XNOR • One multi-bit operand  One single-bit result a = 4’b1001; .. c = |a; // c = 1|0|0|1 = 1

  9. Shift Operators: • >>  shift right • <<  shift left • Result is same size as first operand, always zero filled a = 4’b1010; ... d = a >> 2; // d = 0010 c = a << 1; // c = 0100

  10. Concatenation Operator: {op1, op2, ..}  concatenates op1, op2, .. to single number Operands must be sized !! reg a; reg [2:0] b, c; .. a = 1’b 1; b = 3’b 010; c = 3’b 101; catx = {a, b, c}; // catx = 1_010_101 caty = {b, 2’b11, a}; // caty = 010_11_1 catz = {b, 1}; // WRONG !!

  11. Relational Operators: • >  greater than • <  less than • >=  greater or equal than • <=  less or equal than • Result is one bit value: 0, 1 or x 1 > 0  1 ’b1x1 <= 0  x 10 < z  x

  12. Equality Operators: • ==  logical equality • !=  logical inequality • ===  case equality • !==  case inequality 4’b 1z0x == 4’b 1z0x  x 4’b 1z0x != 4’b 1z0x  x 4’b 1z0x === 4’b 1z0x  1 4’b 1z0x !== 4’b 1z0x  0 Return 0, 1 or x Return 0 or 1

  13. Conditional Operator: • cond_expr ? true_expr : false_expr • Like a 2-to-1 mux .. A 1 Y Y = (sel)? A : B; B 0 sel

  14. Arithmetic Operators: • +, -, *, /, % • If any operand is x the result is x • Negative registers: • regs can be assigned negative but are treated as unsigned reg [15:0] regA; .. regA = -4’d12; // stored as 216-12 = 65524 regA/3 evaluates to 21861

  15. Arithmetic Operators: • Negative integers: • can be assigned negative values • different treatment depending on base specification or not reg [15:0] regA; integer intA; .. intA = -12/3; // evaluates to -4 (no base specification ) intA = -’d12/3; // evaluates to 1431655761 (base specification )

  16. Operator Precedence Use parentheses to enforce your priority

  17. Number Specification There are two types of number specification in Verilog : sized and unsized • Sized numbers: <size>’<radix> <value> Examples: • 8’h ax = 1010xxxx • 12’o 3zx7 = 011zzzxxx111 No of bits Binary  b or B Octal  o or O Decimal  d or D Hexadecimal  h or H Consecutive chars 0-f, x, z

  18. Unsized numbers: Numbers that are specified without a <base format> specification are decimal numbers by default. Numbers that are written without a <size> specification have a default number of bits that is simulator and machine specific(must be at least 32 bits). Examples: 23456 // This is a 32-bit decimal number by default ‘hc3 // This is a 32-bit hexadecimal number ‘o21 // This is a 32-bit octal number

  19. Negative numbers: Negative numbers can be specified by putting a minus sign before the size of a constant number. It is illegal to have a minus sign between <base format> and <number>. Examples: -8’d3 // 8-bit negative number stored as 2’s complement of 3 4’d-2 // Illegal specification

  20. Identifiers and Keywords: • Keywords are special identifiers reserved to define the language constructs. Keywords are in lower case. • Identifiers are made up of alphanumeric characters, the underscore( _ ) and the dollar sign ($) and are case sensitive . • Identifiers start with alphabetic character or an underscore .They can not start with a number or a $ sign . • The $ sign as the first character is reserved for system tasks. Example: reg value; // reg is a keyword ; value is an identifier input clk; // input is a keyword ; clk is an identifier

  21. Data Types • Value Set Verilog supports four values .The four value levels are listed below

  22. Nets • Nets represent connection between hardware elements. • Nets have values continuously driven on them by the outputs of devices that they are connected to. Nets are declared with the keyword wire. • The default value of a net is z. • Registers • Registers represent data storage elements. • Registers retain value until another value is placed onto them. Register data types are declared with the keyword reg. • The default value of a reg is x.

  23. Arrays • Arrays are allowed in Verilog for reg and vector register data types. • Arrays are accessed by <array_name>[<subscript>]. • Mulitidimensionalarrays are not permitted in verilog. Example: reg count[0:7]; //An array of 8 one-bit count register variables.

  24. 5. Memories In digital simulation , one often needs to model register files, RAMs, and ROMs. Memories are modeled in verilog simply as an array of registers. Each element of the array is known as a word. Each word can be one or more bits. It is important to differentiate between n 1-bit registers and one n-bit register. A particular word in memory is obtained by using the address as a memory array subscript. Example: reg [7:0] mem [0:1023] ; //Memory mem with 1k 8-bit words

  25. 6. Parameters Verilog allows constants to be defined in a module by the keyword parameter. Parameters cannot be used as variables. parameter values for each module instance can be overridden individually at compile time.

  26. System Tasks • There are tasks and functions that are used to generate input and output during simulation. Their names begin with a dollar sign ($). • Displaying Information $display is the main system task for displaying values of variables or strings or expressions. Example: $display(“Hello Verilog World “); -- Hello Verilog World • $time $time returns the time as an integer in 64 bits. Example: // To display value of current simulation time 230 $display($time); -- 230

  27. $random $random is used for generating random integer values, this is Verilog build in System Task which returns arandom value. Example: {$random}%11; //returns a random number in the range 0 to 10 • $signed $signed(value) provides interpretation of the value as signed. • $unsigned $unsigned(value) provides interpretation of the value as unsigned

  28. Compiler Directives • `define The `define directive defines a macro with its definition. It is used for text substitution and is very much like the #define in the C programming language. Example: `define MAX_BUS_SIZE 32 ……. reg [`MAX_BUS_SIZE-1:0] add_reg; • `timescale This directive is used to specify the time unit and time precision. The directive is of the form: `timescale time_unit/time_precision

  29. Modeling Styles Within a module a design can be described in the following styles: • Dataflow style • Behavioral style • Structural style • Any mix of above

  30. Dataflow Modeling • Uses continuous assignment statement • Format: assign[ delay ] net = expression; • Example: assignsum = a ^ b; • Delay: Time duration between assignment from RHS to LHS • All continuous assignment statements execute concurrently • Order of the statement does not impact the design

  31. Dataflow Modeling (cont.) • Delay can be introduced Example: assign#2 sum = a ^ b; “#2” indicates 2 time-units No delay specified : 0 (default) • Associate time-unit with physical time `timescaletime-unit/time-precision Example: `timescale 1ns/100 ps • Timescale `timescale1ns/100ps 1 Time unit = 1 ns Time precision is 100ps (0.1 ns) 10.512ns is interpreted as 10.5ns

  32. Dataflow Modeling (cont.) • Example: `timescale 1ns/100ps module HalfAdder (A, B, Sum, Carry); input A, B; output Sum, Carry; assign #3 Sum = A ^ B; assign #6 Carry = A & B; endmodule

  33. Behavioral Modeling • always statement : Sequential Block • Sequential Block: All statements within the block are executed sequentially • When is it executed? Occurrence of an event in the sensitivity list Event: Change in the logical value • Statements with a Sequential Block: Procedural Assignments Delay in Procedural Assignments • Inter-Statement Delay • Intra-Statement Delay

  34. Behavioral Modeling (cont.) • Inter-Assignment Delay • Example: Sum = A ^ B; #2 Carry = A & B; • Delayed execution • Intra-Assignment Delay • Example: Sum = A ^ B; Carry = #2 A & B; • Delayed assignment

  35. Procedural Constructs • Two Procedural Constructs • initial Statement • always Statement • initial Statement : Executes only once • always Statement : Executes in a loop • Example: … initial begin Sum = 0; Carry = 0; end … … always @(A or B) begin Sum = A ^ B; Carry = A & B; end …

  36. Event Control • Event Control • Edge Triggered Event Control • Level Triggered Event Control • Edge Triggered Event Control • @ (posedgeCLK) //Positive Edge of CLK • Curr_State = Next_state; • Level Triggered Event Control • @ (A or B) //change in values of A or B • Out = A & B;

  37. Loop Statements • Loop Statements • Repeat • While • For • Repeat Loop • Example: repeat (Count) sum = sum + 5; • If condition is a x or z it is treated as 0

  38. Loop Statements (cont.) • While Loop • Example: while (Count < 10) begin sum = sum + 5; Count = Count +1; end • If condition is a x or z it is treated as 0 • For Loop • Example: for (Count = 0; Count < 10; Count = Count + 1) begin sum = sum + 5; end

  39. Conditional Statements • if Statement • Format: if (condition) procedural_statement else if (condition) procedural_statement else procedural_statement • Example: if (Clk) Q = 0; else Q = D;

  40. Conditional Statements (cont.) • Case Statement • Example 1: case (X) 2’b00: Y = A + B; 2’b01: Y = A – B; 2’b10: Y = A / B; endcase • Example 2: case (3’b101 << 2) 3’b100: A = B + C; 4’b0100: A = B – C; 5’b10100: A = B / C; //This statement is executed endcase

  41. b sel_b sel a1 n1 sel_n out o1 a a2 sel_a Structural Modeling Structure can be described using • Built-in gate primitives(at the gate-level) • Module instantiation (to create hierarchy) 1. Built-in gate primitives: Example: module comb_circuit(sel,a,b,out); notn1(sel_n, sel); anda1(sel_b, b, sel_b); anda2(sel_a, a, sel); oro1(out, sel_b, sel_a); endmodule

  42. 2. Module instantiation: • The process of creating object from a module template is called instantiation and this objects are called instances. • A module instantiation statement is of the form: module_name instance_name(port_associations); • Example: comb_circuit comb_circuit1( sel, a, b, out);

  43. Design Module Test Bench Test Bench `timescale 1ns/100ps module Top; reg PA, PB; wire PSum, PCarry; HalfAdder G1(PA, PB, PSum, PCarry); initialbegin: LABEL reg [2:0] i; for (i=0; i<4; i=i+1) begin {PA, PB} = i; #5 $display (“PA=%b PB=%b PSum=%b PCarry=%b”, PA, PB, PSum, PCarry); end // for end // initial endmodule Apply Inputs Observe Outputs

  44. Test Bench - Generating Stimulus • Example: A sequence of values initial begin Clock = 0; #50 Clock = 1; #30 Clock = 0; #20 Clock = 1; end

  45. Test Bench - Generating Clock • Repetitive Signals (clock) Clock • A Simple Solution: wire Clock; assign #10 Clock = ~ Clock • Caution: • Initial value of Clock (wire data type) = z • ~z = x and ~x = x

  46. Test Bench - Generating Clock (cont.) • Initialize the Clock signal initialbegin Clock = 0; end • Caution: Clock is of data type wire, cannot be used in an initial statement • Solution: reg Clock; … initial begin Clock = 0; end … always begin #10 Clock = ~ Clock; end forever loop can also be used to generate clock

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