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COE 202 Introduction to Verilog

COE 202 Introduction to Verilog. Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals. Outline. Behavioral Modeling Verilog Operators Behavioral Description of an Adder Always block Procedural Assignment If Statements

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COE 202 Introduction to Verilog

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  1. COE 202Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals

  2. Outline • Behavioral Modeling • Verilog Operators • Behavioral Description of an Adder • Always block • Procedural Assignment • If Statements • Case Statements • Comparator, Arithmetic & Logic Unit • Multiplexor, Encoder, Priority Encoder, Decoder

  3. Behavioral Modeling • Behavioral modeling describes the functionality of a design • What the design will do • Not how the design will be built in hardware • Behavioral models specify the input-output model of a logic circuit and suppress details about its low level internal structure. • Behavioral modeling encourages designers to • Rapidly create a behavioral prototype of a design • Verify its functionality • Use synthesis tool to optimize and map design into a given technology

  4. Data Types for Behavioral Modeling • All variables in Verilog have a predefined type. • There are two families of data types: nets and registers. • Net variables act like wires in physical circuit and establish connectivity between design objects. • Register variables act like variables in ordinary procedural languages – they store information while the program executes. • Register types include: reg, integer, real, realtime, time. • A wire and a reg have a default size of 1 bit. • Size of integer is the size of word length in a computer, at least 32.

  5. Integer Numbers in Verilog • constant numbers can be specified in decimal, hexadecimal, octal, or binary format • integer numbers can be specified as: • Syntax: <size>'<radix><value> (size is in number of bits) • Sized or unsized numbers ( Unsized size is 32 bits ) • In a radix of binary, octal, decimal, or hexadecimal • Radix and hex digits (a,b,c,d,e,f) are case insensitive • Spaces are allowed between the size, radix and value • The character (_) is legal anywhere in a number except as the first character (e.g. 12'b1011_1100_0010, 'hA8, 8'd15) • When <size> is smaller than <value>, then left-most bits of <value> are truncated

  6. Verilog Operators { } concatenation + - * / ** arithmetic % modulus > >= < <= relational ! logical NOT && logical AND || logical OR == logical equality != logical inequality === case equality !== case inequality ? : conditional ~ bit-wise NOT & bit-wise AND | bit-wise OR ^ bit-wise XOR ^~ ~^ bit-wise XNOR & reduction AND | reduction OR ~& reduction NAND ~| reduction NOR ^ reduction XOR ~^ ^~ reduction XNOR << shift left >> shift right

  7. Verilog Operators • Arithmetic Operators: • Each operator takes two operands. + and – could also take a single operand • During synthesis, the + and - operators infer an adder and a subtractor • Xilinx XST software can infer a block multiplier during synthesis for the multiplication operator • /, %, and ** operators usually cannot be synthesized automatically • Shift operators: Four shift operators • >>,<<logical shift right and left (0s inserted from the right or the left) • >>>,<<<arithmetic shift right and left (sign bits are shifted in for the >>> operation and 0's are shifted in for the <<< operation)

  8. Verilog Operators • If both operands of a shift operator are signals, as in a << b, the operator infers a barrel shifter, a fairly complex circuit • If the shifted amount is fixed, as in a << 2, the operation infers no logic and involves only routing of the input signals (can also be done with {} operator) • Examples of shift operations:

  9. Verilog Operators • Relational and equality operators: • Compare two operands and return a 1-bit logical (Boolean) value: either 0 or 1 • 4 relational operators: >, <, <=, and >= • Equality operators: ==, ! =, • The relational operators and the == and ! = operators infer comparators during synthesis

  10. Verilog Operators • Bitwise operators: • 4 basic bitwise operators: & (and), I (or), ^ (xor), and ~(not) • The first three operators require two operands • Negation and xor operation can be combined, as in ~^ or ^~ to form the xnor • operations are performed on a bit-by-bit basis • Ex.: let a, b, and c be 4-bit signals: i.e. wire [3:0] a , b , c ; The statement: assign c = a I b ; is the same as:assign c[3] = a[3] I b[3]; assign c[2] = a[2] I b[2]; assign c[1] = a[1] I b[1]; assign c[0] = a[0] I b[0];

  11. Verilog Operators • Reduction operators: &, I , and ^ operators may have only one operand and then are known as reduction operators. • The single operand usually has an array data type. • The designated operation is performed on all elements of the array and returns a I-bit result. • For example, let a be a 4-bit signal and y be a 1-bit signal: wire [3:0] a ; wire y ; The statement: assign y = I a ; // only one operand is the same as: assign y = a[3] | a[2] | a[1] | a[0] ;

  12. Verilog Operators • Logical operators: && (logical and), II (logical or), and ! (logical negate) • operands of a logical operator are interpreted as false (when all bits are 0's) or true (when at least one bit is 1), and the operation always returns a 1-bit result • Usually used as logical connectives of Boolean expressions, • bitwise and logical operators can be used interchangeably in some situations. • Examples of bitwise and logical operations

  13. Verilog Operators • Conditional operator: ? :takes three operands and its general format is [signal] = [boolean-exp] ? [true-exp] : [false-exp]; • The [boolean-expl] is a Boolean expression that returns true (1) or false ( 0). • Ex.: assign max = (a>b) ? a : b; //max will get the maximum of the signals a and b • The operator can be thought of as a simplified if-then-else statement. • Can be cascaded or nested

  14. Verilog Operators • Concatenation operator: { } • { } combines segments of elements and small arrays to form a large array: wire [7:0] a, ror, srl , sra; assign ror = {a[2:0], a[7:3]} ; // Rotate a to right 3 bits assign srl = {3'b000, a[7:3]} ; // shift a to right 3 bits and insert 0s (logical shift) assign sra = {a[7] , a[7] , a[7] , a[7:3]} ; // arithmeticshift a to right 3 bits

  15. Behavioral Description of an Adder module adder #(parameter width = 4) (output cout, output [width-1:0] sum, input [width-1:0] a, b, input cin); assign {cout, sum} = a + b + cin; endmodule 4-bit operands, 5-bit result { Cout, S } is a 5 bit bus: Cout S[3] S[2] S[1] S[0]

  16. Always Block • always blocks are procedural blocks that contain sequential statements. • Syntax • always @(sensitivity list) begin • end • sensitivity list prevents the always block from executing again until another change occurs on a signal in the sensitivity list. • Level type • always @(a or b or c) • Edge type • always @(posedge clock) • always @(negedge clock)

  17. Procedural Assignment • Assignments inside an always block are called procedural assignments • Can only be used within an always block • Two types : blocking assignment and nonblocking assignment. Basic syntax : • [variable-name] = [expression] ; // blocking assignment • [variable-name] <= [expression] ; // nonblocking assignment • In a blocking assignment, the expression is evaluated and then assigned to the variable immediately, before execution of the next statement (the assignment thus "blocks" the execution of other statements). It behaves like the normal variable assignment in the C language.

  18. Procedural Assignment • In a nonblocking assignment, the evaluated expression is assigned at the end of the always block (the assignment thus does not block the execution of other statements). • The basic rule of thumb is: • Use blocking assignments for a combinational circuit. • Use nonblocking assignments for a sequential circuit • There are two types of variables in Verilog: • wire (all outputs of assign statements must be wire) • reg (all outputs modified in always blocks must be reg) • if-else and case statement are only in always block.

  19. If Statements if (expression) begin ...procedural statements... end else if (expression) begin ...statements... end ...more else if blocks else begin ...statements... end module ALU #(parameter n=8) (output reg [n-1:0] c, input [1:0] s, input [n-1:0] a, b); always @(s or a or b) begin if (s==2'b00) c = a + b; else if (s==2'b01) c = a - b; else if (s==2'b10) c = a & b; else c = a | b; end endmodule

  20. Case Statements case (expression) case_choice1: begin ...statements... end case_choice2: begin ...statements... end ...more case choices blocks... default: begin ...statements... end endcase module ALU2 #(parameter n=8) (output reg [n-1:0] c, input [1:0] s, input [n-1:0] a, b); always @(s or a or b) begin case (s) 2'b00: c = a + b; 2'b01: c = a - b; 2'b10: c = a & b; default: c = a | b; endcase end endmodule

  21. Full Adder module fadd2 (output regS, Cout, input A, B, Cin); always @(A or B or Cin) begin S = (A ^ B ^ Cin); Cout = (A & B) | (A & Cin) | (B & Cin); end endmodule

  22. Comparator module comp #(parameter width=32) (input [width-1:0] A, B, output A_gt_B, A_lt_B, A_eq_B); assign A_gt_B = (A>B); assign A_lt_B = (A<B); assign A_eq_B = (A==B); endmodule

  23. Comparator module comp2 #(parameter width=2) (input [width-1:0] A, B, output regA_gt_B, A_lt_B, A_eq_B); always @(A, B) begin A_gt_B = 0; A_lt_B = 0; A_eq_B = 0; if (A == B) A_eq_B = 1; else if (A > B) A_gt_B = 1; else A_lt_B = 1; end endmodule

  24. Arithmetic Unit module arithmetic #(parameter width=8) (input [width-1:0] A, B, input [1:0] Sel, output reg [width-1:0] Y, output regCout); always @(A or B or Sel) begin case (Sel) 2'b 00 : {Cout,Y} = A+B; 2'b 01 : {Cout,Y} = A-B; 2'b 10 : {Cout,Y} = A+1; 2'b 11 : {Cout,Y} = A-1; default: begin Cout=0; Y=0; end endcase end endmodule

  25. Logic Unit module logic #(parameter width=4) (input [width-1:0] A, B, input [2:0] Sel, output reg[width-1:0] Y); always @(A or B or Sel) begin case (Sel) 3'b 000 : Y = A & B; // A and B 3'b 001 : Y = A | B; // A or B 3'b 010 : Y = A ^ B; // A xor B 3'b 011 : Y = ~A; // 1’s complement of A 3'b 100 : Y = ~(A & B); // A nand B 3'b 101 : Y = ~(A | B); // A nor B default : Y = 0; endcase end endmodule

  26. 2x1 Multiplexer Method 1 module mux2x1 (input b, c, select, output a); assign a = (select ? b : c); endmodule Method 2 module mux2x1 (input b, c, select, output reg a); always@(select or b or c) begin if (select) a=b; else a=c; end endmodule Method 3 module mux2x1 (input b, c, select, output rega); always@(select or b or c) begin case (select) 1’b1: a=b; 1’b0: a=c; endcase end endmodule

  27. Encoder module encoder (output reg[2:0] Code, input [7:0] Data); always @(Data) if (Data==8'b00000001) Code = 0; else if (Data==8'b00000010) Code = 1; else if (Data==8'b00000100) Code = 2; else if (Data==8'b00001000) Code = 3; else if (Data==8'b00010000) Code = 4; else if (Data==8'b00100000) Code = 5; else if (Data==8'b01000000) Code = 6; else if (Data==8'b10000000) Code = 7; else Code = 'bx; endmodule

  28. Priority Encoder modulepriority_encoder(output reg[2:0] Code, output valid_data, input [7:0] Data); assign valid_data = | Data; always @(Data) if (Data[7]) Code = 7; else if (Data[6]) Code = 6; else if (Data[5]) Code = 5; else if (Data[4]) Code = 4; else if (Data[3]) Code = 3; else if (Data[2]) Code = 2; else if (Data[1]) Code = 1; else if (Data[0]) Code = 0; else Code = 'bx; endmodule

  29. Priority Encoder modulepriority_encoder2 (output reg[2:0] Code, output valid_data, input [7:0] Data); assign valid_data = | Data; always @(Data) casex(Data) 8'b1xxxxxxx : Code = 7; 8'b01xxxxxx : Code = 6; 8'b001xxxxx : Code = 5; 8'b0001xxxx : Code = 4; 8'b00001xxx : Code = 3; 8'b000001xx : Code = 2; 8'b0000001x : Code = 1;8'b00000001 : Code = 0; default: Code = 'bx; endcase endmodule Casex treats x values in the inputs as don’t care

  30. Decoder module decoder (output reg[7:0] Data, input [2:0] Code); always @(Code) if (Code == 0 ) Data= 8'b00000001; else if (Code == 1 ) Data= 8'b00000010; else if (Code == 2 ) Data= 8'b00000100; else if (Code == 3 ) Data= 8'b00001000; else if (Code == 4 ) Data= 8'b00010000; else if (Code == 5 ) Data= 8'b00100000; else if (Code == 6 ) Data= 8'b01000000; else if (Code == 7 ) Data= 8'b10000000; else Data = 'bx; endmodule

  31. Seven Segment Display Decoder moduleSeven_Segment_Display (output reg[6:0] Display, input [3:0] BCD); parameter BLANK = 7’b111_1111; parameter ZERO= 7’b000_0001; //abc_defg parameter ONE= 7’b100_1111; parameter TWO= 7’b001_0010; parameter THREE= 7’b000_0110; parameter FOUR= 7’b100_1100; parameter FIVE= 7’b010_0100; parameter SIX= 7’b010_0000; parameter SEVEN= 7’b000_1111; parameter EIGHT= 7’b000_0000; parameter NINE= 7’b000_0100; always @(BCD) case (BCD) 0: Display = ZERO; 1: Display = ONE; 2: Display = TWO; 3: Display = THREE; 4: Display = FOUR; 5 : Display = FIVE; 6: Display = SIX; 7: Display = SEVEN; 8: Display = EIGHT; 9: Display = NINE; default: DISPLAY = BLANK; endcase endmodule

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