Iterative Analog Decoder for a SCCC Alexandre Graell i Amat , Daniele Vogrig , Alberto Perotti, Sergio Benedetto, Guid

1. Iterative Analog Decoder for a SCCCAlexandre Graell i Amat†, Daniele Vogrig‡,Alberto Perotti*, Sergio Benedetto*, Guido Montorsi*, Silvia Soldà‡, Andrea Neviani‡, Andrea Gerosa‡ Politecnico di Torino, Torino, Italy, June 5th, 2006

2. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Outline Motivations Serially concatenated code structure Analog decoder architecture Circuit-level issues Simulation results Programmable interleaver Conclusions and Future Work

3. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Motivations Several functional integrated circuits for small codes are already available in literature, with promising measurement results First analog Turbo-decoders for limited block sizes Implementing large, yet decoders is still an open problem Circuit complexity of fully-parallel analog decoders increase linearly with the block length

4. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” A new class of SCCC

5. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” A new class of SCCC

6. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Code parameters Base interleaver size N’=300 bit Considered interleaver sizes: N=300,600,1200 and 2400 N’x1,2,4,8) Programmable interleaver

7. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Analog Decoder Architecture Fully parallelized analog decoding leads to a prohibitively large chip area a non fully parallel architecture is adopted The decoder core implements one single SISO unit working on a window N’=300 of the code trellis For larger block lengths the module is reused several times to decode each of the constituent codes The decoder performs iterations, but it is fully analog an analog memory to store the extrinsic values after each half iteration is required

8. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Analog Decoder Architecture: decoding procedure

9. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” SISO Scheme

10. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Required precision for the SISO Unit

11. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code”

12. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Input Memory Pseudo-differential memory structure 604 (input bits) x 2 (pseudo diff.) x 2 (banks)= 2416 capacities (7 µm x 9.5 µm) Total Area = 0.16mm2 7 bit DAC (for testing facilities) Current steering topology Settling Time <10ns Estimated Power Consumption: 16 mW

13. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Input Memory (Design Issues) The memory is read at each iteration

14. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Required precision for Extrinsic memory

15. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Extrinsic Memory Interleaver/Deint. Description Next Slides 300 x 2 buffers and 300 x 2 OTAs 8 x 300 x 2 = 4800 capacitors

16. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Extrinsic Memory Switched Capacity Topology C = 25 fF (8 µm x 3 µm ) High Precision required ( Total Error < 10 mV ) Low Mismatch Power ConsuptionBuffer: 1.5 µA x 300 x 2OTA: 3.5 µA x 300 x 2Normalization: 2.0 µA x 300Total: 3.6 mA x 1.8 V = 6.5 mW

17. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Programmable Interleaver To achieve versatility a programmable interleaver is adopted Perfect programmability [Gaudet et. al.] is overly complex for large interleavers In most applications a complete programmability is unnecessary deal only with a fixed number of Interleaver lengths (ex: UMTS, DVB…) We designed a programmable interleaver to cope with the four block lengths

18. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Programmable Interleaver The interleaver can be seen as the cascade of two interleavers, P=PCPR: First, a permutation PC of length N’=300 bit reorders the elements within each subblock is kept fixed for all subblocks At a second stage, a variable permutation PR reorders the (already interleaved) output of the SISO unit writing them to different rows of the extrinsic memory for each subblock variability obtained applying cyclic shifts to a base permutation on the rows

19. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Programmable Interleaver 1st interleaving stage: Fixed PC within each subblock

20. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Interleaver Performance

21. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” Conclusions We presented the design of a fully analog iterative decoder for a serially concatenated code. The decoder allows reconfigurability in both block length (up to 2400 bit) and code rate A low-complexity reconfigurable interleaver to cope with all the interleaver lengths has been designed. Simulation results assessed no performance degradation w.r.t. non-constrained S-random interleavers Circuit non-idealities and mismatch impact on performance were studied to determine the precision required for the analog memories and within the SISO unit

22. “Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code” The talk is over... Any questions?