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Memory. Processor. k. -bit. address bus. MAR. n. -bit. data bus. k. Up to 2. addressable. MDR. locations. Word length =. n. bits. Control lines. R. /. W. ( , MFC, etc.). Figure 5.1. Connection of the memory to the processor. b. b. ¢. b. b. ¢. b. b. ¢. 7.

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  1. Memory Processor k -bit address bus MAR n -bit data bus k Up to 2 addressable MDR locations Word length = n bits Control lines R / W ( , MFC, etc.) Figure 5.1.Connection of the memory to the processor.

  2. b b ¢ b b ¢ b b ¢ 7 7 1 1 0 0 • • • W 0 FF FF A • • • 0 W 1 A 1 Address Memory • • • • • • • • • • • • • • • • • • cells decoder A 2 A 3 • • • W 15 R / W Sense / Write Sense / Write Sense / Write circuit circuit circuit CS Data input /output lines: b b b 7 1 0 Figure 5.2.Organization of bit cells in a memory chip.

  3. 5-bit row address W 0 W 1 32 ´ 32 5-bit memory cell decoder array W 31 Sense / Write circuitry 10-bit address 32-to-1 R / W output multiplexer and CS input demultiplexer 5-bit column address Data input/output Figure 5.3. Organization of a 1K  1 memory chip.

  4. Refresh counter Row Ro w address Cell array decoder latch Row/Column address Column Co lumn Read/Write address circuits & latches decoder counter Clock R A S Mode register Data input Data output C A S and register register timing control R / W C S Data Figure 5.8.Synchronous DRAM.

  5. Clock R / W R A S C A S Address Row Col Data D0 D1 D2 D3 Figure 5.9.Burst read of length 4 in an SDRAM.

  6. Pr ocessor Re gisters Increasing Increasing Increasing size speed cost per bit Primary L1 cache Secondary L2 cache Main memory Magnetic disk secondary memory Figure 5.13.Memory hierarchy.

  7. Main Processor Cache memory Figure 5.14.Use of a cache memory.

  8. Processing units L1 instruction L1 data cache cache Bus interface unit System bus Cache bus Main L2 cache Input/Output memory Figure 5.24. Caches and external connections in Pentium III processor.

  9. Main memory Block 0 Block 1 Block 127 Cache tag Block 0 Block 128 tag Block 1 Block 129 tag Block 127 Block 255 Block 256 Block 257 Block 4095 T ag Block W ord 5 7 4 Main memory address Figure 5.15.Direct-mapped cache.

  10. Main memory Block 0 Block 1 Cache tag Block 0 tag Block 1 Block i tag Block 127 Block 4095 T ag W ord Main memory address 12 4 Figure 5.16. Associative-mapped cache.

  11. Main memory Block 0 Block 1 Cache tag Block 0 Set 0 Block 63 tag Block 1 Block 64 tag Block 2 Set 1 Block 65 tag Block 3 Block 127 tag Block 126 Set 63 Block 128 tag Block 127 Block 129 Block 4095 T ag Set W ord 6 6 4 Main memory address Figure 5.17. Set-associative-mapped cache with two blocks per set.

  12. Memory address Contents A(0,0) 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 A(1,0) 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 A(2,0) 0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 1 A(3,0) A(0,1) 0 1 1 1 1 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 0 1 0 0 A(0,9) 0 1 1 1 1 0 1 0 0 0 1 0 0 1 0 1 A(1,9) 0 1 1 1 1 0 1 0 0 0 1 0 0 1 1 0 A(2,9) A(3,9) 0 1 1 1 1 0 1 0 0 0 1 0 0 1 1 1 T ag for direct mapped T ag for set-associati v e T ag for associati v e (7A00) (7A01) (7A02) (7A03) (7A04) (7A24) (7A25) (7A26) (7A27) Figure 5.18.An array stored in the main memory.

  13. SUM := 0 j:= 0 9 for to do SUM := SUM + A(0,j) end A VE := SUM / 10 for i:= 9 0 do wn to do A(0,i) := A(0,i) / A VE end Figure 5.19. Task for example in Section 5.5.3.

  14. Contents of data cache after pass: Block j = 1 j = 3 j = 5 j = 7 j = 9 i = 6 i = 4 i = 2 i = 0 position 0 A(0,0) A(0,2) A(0,4) A(0,6) A(0,8) A(0,6) A(0,4) A(0,2) A(0,0) 1 2 3 4 A(0,1) A(0,3) A(0,5) A(0,7) A(0,9) A(0,7) A(0,5) A(0,3) A(0,1) 5 6 7 Figure 5.20.Contents of a direct-mapped data cache in Example 5.1.

  15. Contents of data cache after pass: Block j = 7 j = 8 j = 9 i = 1 i = 0 position 0 A(0,0) A(0,8) A(0,8) A(0,8) A(0,0) A(0,1) A(0,1) A(0,9) A(0,1) A(0,1) 1 2 A(0,2) A(0,2) A(0,2) A(0,2) A(0,2) A(0,3) A(0,3) A(0,3) A(0,3) A(0,3) 3 4 A(0,4) A(0,4) A(0,4) A(0,4) A(0,4) A(0,5) A(0,5) A(0,5) A(0,5) A(0,5) 5 6 A(0,6) A(0,6) A(0,6) A(0,6) A(0,6) A(0,7) A(0,7) A(0,7) A(0,7) A(0,7) 7 Figure 5.21. Contents of an associative-mapped data cache in Example 5.1.

  16. Contents of data cache after pass: j = 3 j = 7 j = 9 i = 4 i = 2 i = 0 A(0,0) A(0,4) A(0,8) A(0,4) A(0,4) A(0,0) A(0,1) A(0,5) A(0,9) A(0,5) A(0,5) A(0,1) Set 0 A(0,2) A(0,6) A(0,6) A(0,6) A(0,2) A(0,2) A(0,3) A(0,7) A(0,7) A(0,7) A(0,3) A(0,3) Set 1 Figure 5.22. Contents of a set-associative-mapped data cache in Example 5.1.

  17. k bits m bits Module Address in module MM address ABR DBR ABR DBR ABR DBR Module Module Module n - 1 0 i (a) Consecutive words in a module m bits k bits Address in module Module MM address ABR DBR ABR DBR ABR DBR Module Module Module k 2 - 1 0 i (b) Consecutive words in consecutive modules Figure 5.25.Addressing multiple-module memory systems.

  18. Virtual address from processor Page table base register Page table address Virtual page number Offset + PAGE TABLE Control Page frame bits in memory Page frame Offset Physical address in main memory Figure 5.27.Virtual-memory address translation.

  19. Virtual address from processor Virtual page number Offset TLB Virtual page Control Page frame number bits in memory No =? Yes Miss Hit Page frame Offset Physical address in main memory Figure 5.28.Use of an associative-mapped TLB.

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