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ECE 371 – Unit 16

ECE 371 – Unit 16. ATD – Continued. Sequence Length S8C, S4C, S2C, S1C. Reg 0 Reg 1 Reg 2 Reg 3 Reg 4 Reg 5 Reg 6 Reg 7. MUX. Analog Inputs 8 Channels. S/H. A/D. Fill Pointer CC2,CC1,CC0. CC, CB, CA Mux. Chan. ATD. ATDSTAT0 CC2, CC1, CC0 3 Bit Fill Pointer

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ECE 371 – Unit 16

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  1. ECE 371 – Unit 16 ATD – Continued

  2. Sequence Length S8C, S4C, S2C, S1C Reg 0 Reg 1 Reg 2 Reg 3 Reg 4 Reg 5 Reg 6 Reg 7 MUX Analog Inputs 8 Channels S/H A/D Fill Pointer CC2,CC1,CC0 CC, CB, CA Mux. Chan.

  3. ATD • ATDSTAT0 • CC2, CC1, CC0 • 3 Bit Fill Pointer • Next Result Register to Fill with Converted Value ATDSTAT0 CC2 CC1 CC0 SCF ETORF

  4. ATD • ATD0CTL5 • CC, CB, CA • First Channel to be Converted • Mult = 0 – Same Channel • Mult = 1 – Increment Channel after Conversion ATD0CTL5 0 CC CB CA DJM DSGM SCAN MULT

  5. ATD • ATD0CTL3 • S8C, S4C, S2C, S1C • Length of Conversion Sequence • 0,0,0,0 => 8 Conversions • 0,0,0,1 => 1 Conversion • 0,0,1,0 => 2 Conversions ••• • 1,0,0,0 => 8 Conversion (Maximum Value) ATD0CTL3 0 S8C S2C S1C FRZ2 S4C FIFO FRZ1

  6. ATD • ATD0CTL3 • FIFO • 0 => Reset Fill Pointer to 0 at Start of Sequence • 1 => Do not Reset Fill Pointer ATDCTL3 0 S8C S2C S1C FRZ2 S4C FIFO FRZ1

  7. Example 1 • FIFO=0, CC CB CA =2, MULT = 0 • S8C S4C S2C S1C = 3 • Ch 2 => Result Register 0 • Ch 2 => Result Register 1 • Ch 2 => Result Register 2

  8. Example 1A • FIFO=0, CC CB CA =2, MULT = 1 • S8C S4C S2C S1C = 3 • Ch 2 => Result Register 0 • Ch 3 => Result Register 1 • Ch 4 => Result Register 2

  9. Example 1B • FIFO=1, CC CB CA =2, MULT = 0 • S8C S4C S2C S1C = 2, CC2 CC1 CC0=0 • Ch 2 => Result Register 0 • Ch 2 => Result Register 1 • Ch 2 => Result Register 2 • Ch 2 => Result Register 3

  10. Example 1C • FIFO=1, CC CB CA =2, MULT = 1 • S8C S4C S2C S1C = 2 CC2 CC1 CC0 = 0 • Ch 2 => Result Register 0 • Ch 3 => Result Register 1 • Ch 2 => Result Register 2 • Ch 3 => Result Register 3

  11. ATD • ATD0STAT1 • CCFi = “1” – Result Register i has Data • CCFi = “0” – Result Register I – No Data ATD0STAT1 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0

  12. ATD Example 2 • All Channels are Analog Inputs • ATD0DIEN = 0x00; 0 0 0 0 0 0 0 0 ATD0DIEN IEN6 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN6 IEN1 IEN0 1: DIGITAL INPUT 0: ANALOG INPUT

  13. ATD Example 2 • Enable AD, Software trigger, no interrupt • ATD0CTL2=0x80; 1 0 0 0 0 0 0 0 ATD0CTL2 ASCIF ADPU AFFC ETRIGLE ETRIGEP ADPU AWAI ETRIGE ASCIE

  14. ATD Example 2 • 10 bits, Min S/H Setup, Fastest Clock • ATD0CTL4 = 0x00; 0 0 0 0 0 0 0 0 ATDCTL4 SMP0 SRES8 SMP1 PRS4 PRS3 PRS2 PRS1 PRS0

  15. ATD Example 2 • 3 Conversions , No FIFO • ATD0CTL3 = 0x18; //3 samples s2c=1,s1c=1 ATD0CTL3 0 0 0 1 1 0 0 0 0 S8C S2C S1C FRZ2 S4C FIFO FRZ1

  16. AD Example 2 • Right Justified, unsigned, start with Channel 3, Multiple channels • ATD0CTL5 = 0x13; // Starts Conversion ATD0CTL5 0 0 0 1 0 0 1 1 0 CC CB CA DJM DSGM SCAN MULT

  17. AD Example 2 • Wait for Sequence to Complete • while((ADT0STAT0&0x80)==0); ATDSTAT0 CC2 CC1 CC0 SCF ETORF

  18. AD Example 2 • Read result • unsigned int ch3 = ATD0DR00H); // 16-bit read • unsigned int ch4 = ATD0DR01H; • unsigned int ch5 = ATD0DR02H;

  19. AD Example 2- Modified • Right Justified, unsigned, Chan 3, Mult • ATD0CTL5 = 0x13; // Starts Conversion ATD0CTL5 0 CC CB CA DJM DSGM SCAN MULT

  20. AD Example 2- Modified • Read after result register is full while((ADT0STAT1&0x01)==0); unsigned int ch3 = ATD0DR00H; while((ADT0STAT1&0x02)==0); unsigned int ch4 = ATD0DR01H; while((ADT0STAT1&0x04)==0); unsigned int ch5 = ATD0DR02H; ATD0STAT1 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0

  21. ATD Example 3 • All Channels are Analog Inputs • ATD0DIEN = 0x00; ATD0DIEN IEN6 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN6 IEN1 IEN0 1: DIGITAL INPUT 0: ANALOG INPUT

  22. ATD Example 3 • Enable AD, Ex. Rising Edge Trigger, No Interrupt • ATD0CTL2=0x8C; ATD0CTL2 1 0 0 0 1 1 0 0 ASCIF ADPU AFFC ETRIGLE ETRIGEP ADPU AWAI ETRIGE ASCIE

  23. ATD Example 3 • 10 bits, Min S/H Setup, Fastest Clock • ATD0CTL4 = 0x00; ATDCTL4 SMP0 SRES8 SMP1 PRS4 PRS3 PRS2 PRS1 PRS0

  24. ATD Example 3 • 1 Conversion , No FIFO • ATD0CTL3 = 0x08; //1 samples s2c=0,s1c=1 ATD0CTL3 0 0 0 0 1 0 0 0 0 S8C S2C S1C FRZ2 S4C FIFO FRZ1

  25. AD Example 4 – SCAN=1 • Right Justified, unsigned, Chan 3, Scan • ATD0CTL5 = 0x23; // Starts Conversion ATD0CTL5 0 0 1 0 0 0 1 1 0 CC CB CA DJM DSGM SCAN MULT

  26. AD Example 4 – SCAN=1 • Wait for Each Conversion to Complete while((ADT0STAT0&0x80)==0); unsigned int ch3 = ATD0DR00H; // 16-bit read ---------- while((ADT0STAT0&0x80)==0); unsigned int ch3 = ATD0DR00H; // 16-bit read ----------- while((ADT0STAT0&0x80)==0); unsigned int ch3 = ATD0DR00H; // 16-bit read ATDSTAT0 CC2 CC1 CC0 SCF ETORF

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