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VHDL

V HSIC H ardware D escription L anguage. V ery H igh S peed I ntegrated C ircuits. VHDL. entidade. reg4. d0. s0. s1. d1. portas de saída. d2. s2. portas de entrada. d3. s3. en. clk. entity reg4 is port (d0, d1, d2, d3, en, clk : in bit;

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VHDL

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  1. VHSIC Hardware Description Language Very High Speed Integrated Circuits VHDL

  2. entidade reg4 d0 s0 s1 d1 portas de saída d2 s2 portas de entrada d3 s3 en clk entity reg4 is port (d0, d1, d2, d3, en, clk : in bit; s0, s1, s2, s3 : out bit ); end entity reg4; declaração da entidade

  3. A descrição da implementação interna duma entidade chama-se corpo arquitectural. Uma entidade pode ter vários corpos arquitecturais que correspondem às implementação alternativas. Corpo arquitectural comportamental estrutural misto descreve o funcionamento de um modo abstracto; só inclui atribuições de sinais concorrentes e processos que especificam acçõessequenciais a executar. descreve que subsistemas compõem a entidade e como estes são interligados. algumas partes da entidade são descritas como comportamentais enquanto outras são descritas de modo estrutural.

  4. Descrição comportamental architectureBehavioralofreg4is begin process (d0, d1, d2, d3, en, clk) is begin if en = '1' and clk = '1' then s0 <= d0; s1 <= d1; s2 <= d2; s3 <= d3; endif; endprocess; endBehavioral;

  5. Descrição estrutural bit0 latch d d0 s s0 clk bit1 latch d d1 s s1 clk bit2 latch d d2 s s2 clk bit3 latch d d3 s s3 clk gate and2_gate en x z clk y

  6. Descrição estrutural bit0 latch d d0 s s0 clk bit1 latch d d1 s s1 clk bit2 latch d d2 s s2 clk bit3 latch d d3 s s3 clk x z en and2_gate clk y entity latch is port ( d, clk : in bit; s : out bit); end latch; architecture beh of latch is begin latch_beh: process (clk, d) is begin if clk = '1' then s <= d; endif; endprocess latch_beh; end beh; entity and2_gate is Port ( x, y : in bit; z : out bit); end and2_gate; architecture beh of and2_gate is begin z <= x and y; end beh;

  7. Descrição estrutural bit0 latch d d0 s s0 clk bit1 latch d d1 s s1 clk bit2 latch d d2 s s2 clk bit3 latch d d3 s s3 clk x z en and2_gate clk y entity latch is port ( d, clk : in bit; s : out bit); end latch; architecture beh of latch is begin process (clk, d) is begin if clk = '1' then s <= d; endif; endprocess; end beh; entity and2_gate is Port ( x, y : in bit; z : out bit); end and2_gate; architecture beh of and2_gate is begin z <= x and y; end beh;

  8. instâncias de componentes entity reg4 is Port ( d0, d1, d2, d3, en, clk : in bit; s0, s1, s2, s3 : out bit); end reg4; architecture estrutural of reg4 is signalint_clk : bit; begin bit0:entity work.latch(beh) portmap (d0, int_clk, s0); bit1:entity work.latch(beh) portmap (d1, int_clk, s1); bit2:entity work.latch(beh) portmap (d2, int_clk, s2); bit3:entity work.latch(beh) portmap (d3, int_clk, s3); gate:entity work.and2_gate(beh) portmap (en, clk, int_clk); end estrutural; int_clk

  9. library IEEE; use IEEE.std_logic_1164.all; entity design_module_ent is port ( input1,input2,input3,input4 : in STD_LOGIC; output1,output2,output3: out STD_LOGIC ); end design_module_ent; architecture design_module_ent_arch of design_module_ent is component and_ent port ( input1,input2 : in STD_LOGIC; output1: out STD_LOGIC ); end component; begin logic_AND_1 : and_ent PORT MAP (input1,input2,output1); logic_AND_2 : and_ent PORT MAP (input2,input3,output2); logic_AND_3 : and_ent PORT MAP (input3,input4,output3); end design_module_ent_arch;

  10. input1 output1 input2 output2 input3 output3 input4 library IEEE; use IEEE.std_logic_1164.all; entity design_module_ent is port ( input1,input2,input3,input4 : in STD_LOGIC; output1,output2,output3: out STD_LOGIC ); end design_module_ent; architecture design_module_ent_arch of design_module_ent is component and_ent port ( input1,input2 : in STD_LOGIC; output1: out STD_LOGIC ); end component; begin logic_AND_1 :and_entPORT MAP (input1,input2,output1); logic_AND_2 : and_ent PORT MAP (input2,input3,output2); logic_AND_3 : and_ent PORT MAP (input3,input4,output3); end design_module_ent_arch;

  11. A  SUM B CARRY library IEEE; use IEEE.std_logic_1164.all; entity adder1 is port ( A: in STD_LOGIC; B: in STD_LOGIC; SUM: out STD_LOGIC; CARRY: out STD_LOGIC ); end adder1; architecture adder1_arch of adder1 is begin -- <<enter your statements here>> SUM <= A xor B; CARRY <= A and B; end adder1_arch;

  12. library IEEE; use IEEE.std_logic_1164.all; entity adder1 is port ( A: in STD_LOGIC; B: in STD_LOGIC; SUM: out STD_LOGIC; CARRY: out STD_LOGIC ); end adder1; architecture adder1_arch of adder1 is begin -- <<enter your statements here>> SUM <= A xor B; CARRY <= A and B; end adder1_arch; Z OR entity FULLADD is port (A, B, CIN : in bit; SUM, CARRY : out bit); end FULLADD; architecture STRUCT of FULLADD is signal I1, I2, I3 : bit; component adder1 port(A,B : in bit; SUM, CARRY : out bit); end component; component ORGATE port(A,B : in bit; Z : out bit); end component; begin u1:adder1 port map(A,B,I1,I2); u2:adder1 port map(I1,CIN,SUM,I3); u3:ORGATE port map(I2,I3,CARRY); end STRUCT; library IEEE; use IEEE.std_logic_1164.all; entity ORGATE is port ( A: in STD_LOGIC; B: in STD_LOGIC; Z: out STD_LOGIC ); end ORGATE; architecture ORGATE_arch of ORGATE is begin -- <<enter your statements here>> Z <= A or B; end ORGATE_arch;

  13. A B A (A) A (I1)   SUM (SUM) CARRY SUM (I1) OR B (B) B (CIN) SUM CARRY (I3) CARRY (I2) CIN entity FULLADD is port (A, B, CIN : in bit; SUM, CARRY : out bit); end FULLADD; architecture STRUCT of FULLADD is signal I1, I2, I3 : bit; component adder1 port(A,B : in bit; SUM, CARRY : out bit); end component; component ORGATE port(A,B : in bit; Z : out bit); end component; begin u1:adder1 port map(A,B,I1,I2); u2:adder1 port map(I1,CIN,SUM,I3); u3:ORGATE port map(I2,I3,CARRY); end STRUCT; I2 I3 CARRY (CARRY)

  14. SW1 SW2 SW3 LED1 LED2 LED3 LED4

  15. switchers(2) switchers(1) switchers(0) LCD_struc LEDs : out std_logic_vector(3 downto 0); 48 MHz Divider clk48 rst rst loc_clk  1 Hz internal_clock CLK RESET S3 LED_SW SW1 SW2 SW3 S2 S1 MEF LED1 LED2 LED3 LED4 switchers : in std_logic_vector (2 downto 0); LEDs(0) LEDs(1) LEDs(2) LEDs(3) L1 L2 L3 L4 entity LCD_struc is Port ( switchers : in std_logic_vector(2 downto 0); LEDs : out std_logic_vector(3 downto 0); clk48 : in std_logic; rst : in std_logic); end LCD_struc; architecture Behavioral of LCD_struc is component LED_SW PORT (CLK,RESET,SW1,SW2,SW3: IN std_logic; LED1,LED2,LED3,LED4 : OUT std_logic); end component; component Divider Port ( clk48 : in std_logic; rst : in std_logic; loc_clk : out std_logic); end component; signal internal_clock : STD_LOGIC; begin FSM : Divider port map(clk48,rst,internal_clock); led_control : LED_SW port map(internal_clock,rst,switchers(2),switchers(1),switchers(0), LEDs(0),LEDs(1),LEDs(2),LEDs(3)); end Behavioral; LCD_struc

  16. switchers(2) switchers(1) switchers(0) LCD_struc LEDs : out std_logic_vector(3 downto 0); 48 MHz Divider clk48 rst rst loc_clk  1 Hz internal_clock CLK RESET S3 LED_SW SW1 SW2 SW3 S2 S1 MEF LED1 LED2 LED3 LED4 switchers : in std_logic_vector (2 downto 0); LEDs(0) LEDs(1) LEDs(2) LEDs(3) L1 L2 L3 L4 entity LCD_struc is Port ( switchers : in std_logic_vector(2 downto 0); LEDs : out std_logic_vector(3 downto 0); clk48 : in std_logic; rst : in std_logic); end LCD_struc; architecture Behavioral of LCD_struc is component LED_SW PORT (CLK,RESET,SW1,SW2,SW3: IN std_logic; LED1,LED2,LED3,LED4 : OUT std_logic); end component; component Divider Port ( clk48 : in std_logic; rst : in std_logic; loc_clk : out std_logic); end component; signal internal_clock : STD_LOGIC; begin FSM : Divider port map(clk48,rst,internal_clock); led_control : LED_SW port map(internal_clock,rst,switchers(2),switchers(1),switchers(0), LEDs(0),LEDs(1),LEDs(2),LEDs(3)); end Behavioral; connection

  17. entity my_gate is port ( x1: in STD_LOGIC; x2: in STD_LOGIC; x3: in STD_LOGIC; y: out STD_LOGIC ); architecture my_gate_arch of my_gate is begin -- <<enter your statements here>> y <= not (x1 and x2 and x3); end my_gate_arch; configuration config_and of and_ent is for and_ent_arch end for; end config_and; VHDL entity architecture configuration

  18. library IEEE; use IEEE.std_logic_1164.all; entity and_ent is port ( input1: in STD_LOGIC; input2: in STD_LOGIC; output1: out STD_LOGIC ); end and_ent; architecture and_ent_arch of and_ent is begin Process(input1,input2) begin if ((input1 = '1') AND (input2 = '1')) then output1 <= '1'; else output1 <= '0'; end if; end Process; end and_ent_arch; architecture and_ent_arch1 of and_ent is begin output1 <= input1 and input2; end and_ent_arch1; configuration config_and of and_ent is for and_ent_arch end for; end config_and; configuration config_and of and_ent is for and_ent_arch1 end for; end config_and;

  19. library IEEE; use IEEE.std_logic_1164.all; entity and_ent is port ( input1: in STD_LOGIC; input2: in STD_LOGIC; output1: out STD_LOGIC ); end and_ent; architecture and_ent_arch of and_ent is begin Process(input1,input2) begin if ((input1 = '1') AND (input2 = '1')) then output1 <= '1'; else output1 <= '0'; end if; end Process; end and_ent_arch; architecture and_ent_arch1 of and_ent is begin output1 <= input1 and input2; end and_ent_arch1; configuration config_and of and_ent is for and_ent_arch end for; end config_and;

  20. STD_LOGIC • '1' - logical 1 • '0' - logical 0 • 'H' – weak 1 • 'L' – weak 0 • 'X' – unknown • 'U' – uninitialized • 'Z' – high impedance • '-' – don't care • 'W' – weak unknown

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