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VHDL

VHDL. ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning. VHDL Tools. Hardware Description Language Tools Text Editor Design Entry Compiler Syntax Simulator Test Bench Functional Verification Synthesis tool Libraries Target Technology. Entity

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VHDL

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  1. VHDL ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning

  2. VHDL Tools • Hardware Description Language Tools • Text Editor • Design Entry • Compiler • Syntax • Simulator • Test Bench • Functional Verification • Synthesis tool • Libraries • Target Technology 311_10

  3. Entity Component interface Inputs Outputs Architecture Structural Dataflow Behavioral VHDL Model 311_10

  4. Propagation Delays 311_10

  5. Std_Logic_Vectors 311_10

  6. Multiplexers 311_10

  7. Design Hierarchy 311_10

  8. 4-bit Ripple-Carry Adder entity Adder4 is port(A, B: in bit_vector(3 downto 0); Ci: in bit; S: out bit_vector(3 downto 0); Co: out bit); end Adder4; 311_10

  9. VHDL Types • Predefined Types • IEEE Standard Logic 311_10

  10. VHDL Operators & concatenation 311_10

  11. VHDL Libraries and Packages • library IEEE; • use IEEE.std_logic_1164.all; • Types std_logic and std_logic_vector • use IEEE.std_logic_unsigned.all; • Overloaded operators • Conversion functions • use work.project3_gates.all; 311_10

  12. Project 3 VHDL • Structural Description • Entity • Structural Architecture • Package • Component declarations • Dataflow descriptions 311_10

  13. Project 3 Xilinx • New Project • Top-Level Source Type → HDL • Project→ New Source • VHDL Module • Project→ Add Copy of Source • project3_gates.vhd 311_10

  14. New Source 311_10

  15. 311_10

  16. Summary • Entity • Architecture • Structural • Dataflow • Behavioral • Types • Operators • Libraries and Packages 311_10

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