ELEC1700 Computer Engineering 1 Week 9 Monday lecture Flip-flops and state machines

1. ELEC1700Computer Engineering 1Week 9 Monday lectureFlip-flops andstate machines Semester 1, 2013

2. Edge-triggered flip-flops D flip-flops J-K flip-flops Analysis of state machines Flip-flops and state machines

3. EN Latches Gated S-R latch When enabled (EN is HIGH) • S=set (Q→1) • R=reset (Q→0) • Latch “remembers” Q when EN goes LOW Gated D latch • Q follows D when enable is asserted (EN is HIGH) • Latch “remembers” Q when EN goes LOW

4. Edge-triggered flip-flops • Like latches, flip-flops are also bistable devices • But output of a flip-flop only changes at a specified time • “triggering” time is specified by a clock(CLK) signal • either rising edge ↑ or falling edge ↓ of clock • We consider 3 flip-flop types: S-R, D, and J-K Positive edge-triggered (CLK ↑) Negative edge-triggered (CLK ↓)

5. Edge-triggering • Pulse transition detector produces short enable spike on rising edge of CLK • Gated S-R latch “sees” S and R only on CLK ↑ transition

6. Positive edge-triggered S-R flip-flop Ignore these additional inputs for now Week09Mon_SRFF.circ

7. Positive edge-triggered S-R flip-flop

8. Positive edge-triggered S-R flip-flop Sketch the outputs Q and Q’ for the CLK, S and R signals shown Output Q is initially LOW

9. Edge-triggered flip-flops D flip-flops J-K flip-flops Analysis of state machines Flip-flops and state machines

10. Positive edge-triggered D flip-flop Week09Mon_DFF.circ Positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter Positive edge-triggered D flip-flop — circuit symbol D flip-flop stores one data bit (0 or 1) Bit at input D is stored by flip-flop on rising edge of CLK

11. Positive edge-triggered D flip-flop Sketch the output Q for the CLK and D signals shown Output Q is initially LOW

12. D flip-flop – excitation table D QN QN+1 0 0 0 0 1 0 1 0 1 1 1 1 QN QN+1 0 0 0 1 1 0 1 1 D Next-state table Excitation table 0 1 0 1 QN = state of flip-flop before clock edge (also written simply as Q) QN+1 = state of flip-flop after clock edge (also written as Q+) Next-state table says: “how does Q change on next clock edge?” Excitation table says: “what input D is needed so that Q makes a particular transition on next clock edge?”

13. D=1 Q=0 Q=1 D=0 D=1 D=0 D flip-flop – state transition diagram State transition diagram (or simply state diagram) ― a graphical method to show what happens on next clock edge 2 flip-flops → 4 states 3 flip-flops → 8 states, etc. • Each bubble is a distinct state of the circuit • Edges (arrows) are transitions between states • Inputs causing transitions between states label the edges

14. Edge-triggered flip-flops D flip-flops J-K flip-flops Analysis of state machines Flip-flops and state machines

15. Edge-triggered J-K flip-flop • Like an S-R flip-flop with J = SET and K = RESET • J=K=1 causes flip-flop to toggle instead of invalid • 0 → 1 • 1→ 0

16. Edge-triggered J-K flip-flop J-K flip-flop is versatile and very widely used Week09Mon_JKFF.circ Remember: J = SET K = RESET and J=K=1 causes Q to toggle

17. Edge-triggered J-K flip-flop Sketch the output Q for the CLK, J and K signals shown Output Q is initially LOW Note that this is a negative edge-triggered device

18. J-K flip-flop – excitation table Next-state table Excitation table J K QN QN+1 0 0 00 0 0 11 0 1 00 0 1 10 1 0 01 1 0 11 1 1 01 1 1 10 QN QN+1 J K 0 0 0 X 00, 01 (hold or reset) 0 1 1 X 10, 11 (set or toggle) 1 0 X 1 01, 11 (reset or toggle) 1 1 X 0 00, 10 (hold or set) hold reset set toggle X means “don’t care” i.e. 0 or 1

19. 1X 0X 0 1 X0 X1 J-K flip flop – state diagram Using compact notation: • write 1X instead of JK=1X • meaning: JK=10 or 11 causes transition from Q=0 to Q=1

20. J-K with asynchronous Preset and Clear EN=0 → clock ignored set: active-LOW reset: active-HIGH In Logisim: set/reset pins have no effect if undefined (not connected) set reset EN • S/R, D and J/K inputs are synchronous inputs • data is transferred from inputs to flip-flop outputs only on clock edge • Asynchronous inputs affect state of flip-flop independent of CLK • preset (PRE) sets flip-flop when active • clear (CLR) resets flip flop when active • PRE and CLR usually active-LOW

21. J-K flip-flop with Preset and Clear CLK J K PRE/ CLR/ Q

22. Edge-triggered flip-flops D flip-flops J-K flip-flops Analysis of state machines Flip-flops and state machines

23. State machines • State machines also known as sequential machines (or sequential circuits) • External inputs I0,…,Im • Memory block = set of flip-flops, with inputs Y0,…,Yp • Synchronous circuit means all flip-flops connected to one clock • Present state of machine: state variables Q0,…,Qx • Next state: determined by inputs and present state

24. Analysis and design of state machines Analysis given a circuit diagram, determine what function the circuit performs circuit diagram  state transition table  state diagram Design given a desired function, design the required circuit specification  state diagram  next-state table  excitation table  circuit diagram

25. Analysis of state machines: Example What function does this circuit perform? Decoded 7-segment display J1 Q1 K1 J0 Q0 K0 Let’s construct the state diagram to find out

26. Transition table By inspection of circuit diagram: Q1 Q0J1=Q0’ K1=Q0’ J0=1 K0=1 Q1+ Q0+ 0 0 1 1 1 1 1 1 0 1 0 0 1 1 0 0 1 0 1 1 1 1 0 1 1 1 0 0 1 11 0

27. State diagram • Circuit moves through states 00,11,10,01,… • Decimal numbers displayed: 0,3,2,1,0,… • Circuit is a 2-bit down-counter 00 11 01 10 The edges have no labels, since circuit has no external input (apart from CLK)

28. Logisim verification Week09Mon_mystery.circ