ELEC1700 Computer Engineering 1 Week 11 Monday lecture Programmable logic Semester 1, 2013

1. ELEC1700Computer Engineering 1Week 11 Monday lectureProgrammable logic Semester 1, 2013

2. Introduction to programmable logic CPLDs FPGAs VHDL Programmable logic

3. Programmable logic • Programmable logic = “configurable” logic • Contrast with 74-series ICs, which provide fixed-function logic • PLDs = programmable logic devices • SPLD = simple PLD • CPLD = complex PLD • FPGAs = field-programmable gate arrays Just the basics in ELEC1700— ELEC3720 Programmable Logic Design

4. Design flow • Design entry • Schematic capture • Hardware description language (VHDL) • Functional simulation • Does the circuit work? • Ignore gate propagation delays • Synthesis • Design translated into a “netlist” • Shows how gates are connected • Implementation • Map design to specific target device • Timing simulation • Is design still OK with gate delays?

5. Design entry VHDL text entry Schematic entry

6. Download • Bitstream configures “target device” = CPLD or FPGA Altera MAX7000 100-pin CPLD Altera Stratix 956-pin FPGA

7. Computer-aided design (CAD) tools large numbers of programmable/configurable elements in CPLDs and FPGAs simplification of Boolean functions is just one part of the overall design; other factors: ability to split large designs between engineers documentation design correctness efficient use of resources in CPLD or FPGA clear need for computer-aided design tools schematic capture hardware description languages such as VHDL (= VHSIC HDL) VHSIC = Very High-Speed Integrated Circuits VHSIC program funded by U.S. Department of Defense in 1970s—1980s the other major HDL is Verilog

8. Introduction to programmable logic CPLDs FPGAs VHDL Programmable logic

9. Basic AND/OR structure of configurable SOP

10. SOP expression

11. Simplified notation

12. Simplified notation—Example

13. Simple PLD block diagram • PAL16V8—a typical SPLD = simple PLD • Up to 8 product terms per output • ≈300 equivalent logic gates

14. CPLD block diagram • CPLD = complex PLD • LAB = logic array block • PIA = programmable interconnect array • Common to have 16 logic outputs per LAB • Manufacturers specify CPLD density in number of LABs • Up to 1000+ LABs per package

15. Altera MAX 7000 series CPLD • Altera EPM7064SLC44 CPLD • 4 LABs @ 16 macrocells each • 1250 usable gates ≈$13 • 1¢ per gate

16. Simplified Altera 7000 series macrocell

17. Shared expanders • Shared expanders increase number of product terms generated by a macrocell

18. Shared expander

19. Parallel expanders

20. 0  Y = X 1  Y = X’ Y X Macrocell in Altera MAX 7000 family of CPLDs

21. Macrocell: SOP logic function • Macrocell configured for generation of a combinational (SOP) logic function • Red indicates data path

22. Macrocell: registered logic function • Macrocell configured for generation of a registered (sequential) logic function • Red indicates data path

23. Introduction to programmable logic CPLDs FPGAs VHDL Programmable logic

24. Field-programmable gate arrays (FPGAs) CPLD— small number of large, complex logic blocks FPGA — large number of small, simple logic blocks

25. FPGA logic blocks “field-programmable” means devices are configured by a designer rather than the device manufacturer simplest type of logic block is a lookup table (LUT) implemented here using multiplexers and one-bit storage cells (0/1) inputs x1 and x2 drive select inputs on multiplexers any 2-input logic function can be built by programming LUT with appropriate bits easily extended to 3-inputs, 4-inputs, … x1 0/1 0/1 f 0/1 0/1 x2

26. 2-input lookup table (LUT) x1 1 f x1 x2 1 0 x1 0 0 1 0 0 1 0 0 f f 0 1 0 0 1 x2 1 1 1 1 x2 Truth table Implementation using 2-input LUT Simplified representation Line colors show what values of x1 and x2 here? x1 = x2 = 0

27. Section of a programmed FPGA x3 f 0 0 0 1 1 0 0 0 1 1 0 1 x1 x1 x2 f1 f1 f2 f x2 x2 x3 f2 • = potential connection X = actual connection

28. Routing in an FPGA • Clearly a task well-suited for CAD tools! • Altera Cyclone 12K LE256 FPGA • 12,060 logic blocks + 239,616bits of RAM ≈$37 • 0.3¢ per logic output • 0.02¢ per bit of RAM

29. Introduction to programmable logic CPLDs FPGAs VHDL Programmable logic

30. Why use VHDL? power and flexibility VHDL provides powerful language constructs succinct code descriptions of complex designs supports design libraries, re-usable components and hierarchies device-independent design permits design creation before choosing a device portability between simulators and synthesis tools it’s an IEEE standard (IEEE 1076.3) VHDL design is “future-proof” as it is supported by: many synthesis tools (Altera Quartus II, Xilinx Foundation Series, …) many vendors/devices (Altera MAX7000 CPLD, Xilinx XC4000 FPGA,…)

31. What does VHDL look like? x1 x3 f x2 g x4 entity example_1 is port ( x1, x2, x3, x4 : in std_logic; f, g : out std_logic); end example_1; architecture boolean_eqns of example_1 is begin f <= (x1 and x3) or (not x3 and x2); g <= (not x3 or x1) and (not x3 or x4); end boolean_eqns; • entity — describes inputs and outputs • architecture — describes internal operation of the entity

32. A second VHDL example 3 3 3 w0 f w1 entity example_2 is port ( w0, w1 : in std_logic_vector (2 downto 0) s : in std_logic; f : out std_logic_vector(2 downto 0)); end example_1; architecture behavior of example_2 is begin process (w0,w1,s) begin case s is when ‘0’ => f <= w0; when others => f <= w1; end case; end process; end behavior; 3-bit 2-input multiplexer s • mux has 3+3+1 = 7 inputs  27 = 128 rows in truth table description • VHDL description is almost self-explanatory • Code is easily extended to wider buses and more inputs