Next in line…

1. Next in line… • Advance techniques in design optimisations. • Introduction to synthesis tools. • Design flow using FPGA and ASIC. • Summary.

2. Optimisation while building a counter process begin wait until clk’event and clk=’1’ ; if (count = some_value) then count <= 0 ; else count <= count + 1 ; end if ; end process ; • Comparator is checking 2 variables, value[3:0] and q[3:0].

3. Optimisation of counter: Now we count to zero process begin wait until clk’event and clk=’1’ ; if (count = 0) then count <= some_value ; else count <= count - 1 ; end if ; end process ; • Slightly different syntax (identical functionality): • Comparator is checking 1 variable and 1 constant, therefore much smaller.

4. Advanced: Think in hardware 1. • Turns out that… • 1 is better than 2 using ASIC library from vendor A; • 2 is better than 1 (10 times smaller) using ASIC library from vendor B; • 1 is the almost the same as 2 using FPGA library from vendor C! begin LE <= '1' when (data1 <= data2) else '0'; end EG ; 2. process (data1, data2) variable x, y, z : unsigned (64 downto 0); begin x := '0' & unsigned(data1); y := '0' & unsigned(data2); z := y - x; if (z(64) = '0') then LE <= '1'; else LE <= '0'; end if; end process;

5. Advanced: Think in hardware • Destination architecture • Standard cells available • “Fit” with synthesizers • How good the library designer is

6. Commercial Synthesis Tools • Leonardo Spectrum (www.exemplar.com) • FPGA Express (www.synopsys.com) • Synplicity Pro (www.synplicity.com) • Cadance, Avant! • http://dir.yahoo.com/Business_and_Economy/Business_to_Business/Computers/Software/CAD_CAM/IC_Design/

7. Leonardo Spectrum Leonardo and Spectrum is two parts. Spectrum is the synthesis engine, text and TCL scripts driven. Spectrum is source compatible with AutologicII. Leonardo is the graphical front end. Level 3 handles ASIC synthesis.

9. FPGA Express • For FPGA! • Used in Xilinx Foundation as their default synthesizer. • Integrated into Foundation, so handled by Project Manager. • Altera just switched to Leonardo Spectrum. • ASIC synthesis: Physical Compiler

11. Completing Design Flow in FPGA Can I see my design placed inside FPGA in some way? library IEEE; use IEEE.std_logic_1164.all; entity counter is port ( clk : in std_logic ; value1 : in integer range 0 to 255; count : out integer range 0 to 255); end counter ; architecture EG of counter is signal counting : integer range 0 to 255; begin process begin count <= counting; wait until clk'event and clk='1'; if (counting = 0) then counting <= value1 ; else counting <= counting - 1 ; end if ; end process ; end EG ;

12. Your design is here

13. Advantages in Synthesis to PLDs and FPGAs • Flexibility • Portability • Fast design cycle • Some abstractions • No need for verifications

14. Disadvantages in Synthesis • Strict coding style for efficient implementation • Buried timing • Less efficient use to silicon area • Only half way to solution • No easy verifications

15. Other Approaches • Pre-synthesis analysis • Post-synthesis analysis • Syntax parsers • Templates • Formal descriptions • Behavioural descriptions • System descriptions

16. Conclusions • Basic HDL structures for fundamental digital system components. • Synthesize for low power, small area. • Automatic synthesis tools cannot replace clever syntax & analysis from designers. • Good tools + good designer = good implementation • Tools will get clever, but nowhere as good as us.

17. Sources • Simon Leung • 44