Chapters 8

1. Chapters 8 (partial coverage)

2. Interfacing Processors and Peripherals • I/O Design affected by many factors (expandability, resilience) • Performance: — access latency — throughput — connection between devices and the system — the memory hierarchy — the operating system • A variety of different users (e.g., banks, supercomputers, engineers)

3. I/O • Important but neglected “The difficulties in assessing and designing I/O systems have often relegated I/O to second class status” “courses in every aspect of computing, from programming to computer architecture often ignore I/O or give it scanty coverage” “textbooks leave the subject to near the end, making it easier for students and instructors to skip it!” • GUILTY! — we won’t be looking at I/O in much detail — be sure and read Chapter 8 in its entirety. — you should probably take a networking class!

4. I/O Devices • Very diverse devices — behavior (i.e., input vs. output) — partner (who is at the other end?) — data rate

5. I/O Device Examples Device Behavior Partner Data Rate (KB/sec) Keyboard Input Human 0.01 Mouse Input Human 0.02 Line Printer Output Human 1.00 Floppy disk Storage Machine 50.00 Laser Printer Output Human 100.00 Optical Disk Storage Machine 500.00 Magnetic Disk Storage Machine 5,000.00 Network-LAN Input or Output Machine 20 – 1,000.00 Graphics Display Output Human 30,000.00

6. I/O Example: Disk Drives • To access data: — seek: position head over the proper track (8 to 20 ms. avg.) — rotational latency: wait for desired sector (7200 / RPM) — transfer: grab the data (one or more sectors) 2 to 15 MB/sec

7. Example • 512 byte sector, rotate at 5400 RPM, advertised seeks is 12 ms, transfer rate is 4 MB/sec, controller overhead is 1 ms, queue idle so no service time • Disk Access Time = Seek time + Rotational Latency + Transfer time + Controller Time + Queueing Delay • Disk Access Time = 12 ms + 0.5 / 5400 RPM + 0.5 KB / 4 MB/s + 1 ms + 0 • Disk Access Time = 12 ms + 0.5 / 90 RPS + 0.125 / 1024 s + 1 ms + 0 • Disk Access Time = 12 ms + 5.5 ms + 0.1 ms + 1 ms + 0 ms • Disk Access Time = 18.6 ms • If real seeks are 1/3 advertised seeks, then its 10.6 ms, with rotation delay at 50% of the time!

8. I/O Example: Buses • Shared communication link (one or more wires) • Difficult design: — may be bottleneck — length of the bus — number of devices — tradeoffs (buffers for higher bandwidth increases latency) — support for many different devices — cost • Types of buses: — processor-memory (short high speed, custom design) — backplane (high speed, often standardized, e.g., PCI) — I/O (lengthy, different devices, standardized, e.g., SCSI) • Synchronous vs. Asynchronous — use a clock and a synchronous protocol, fast and small but every device must operate at same rate and clock skew requires the bus to be short — don’t use a clock and instead use handshaking

9. Processor Input Control Memory Datapath Output What is a bus? A Bus Is: • shared communication link • single set of wires used to connect multiple subsystems • A Bus is also a fundamental tool for composing large, complex systems • systematic means of abstraction

10. Buses

11. Memory Processer Advantages of Buses • Versatility: • New devices can be added easily • Peripherals can be moved between computersystems that use the same bus standard • Low Cost: • A single set of wires is shared in multiple ways I/O Device I/O Device I/O Device

12. Memory Processer Disadvantage of Buses • It creates a communication bottleneck • The bandwidth of that bus can limit the maximum I/O throughput • The maximum bus speed is largely limited by: • The length of the bus • The number of devices on the bus • The need to support a range of devices with: • Widely varying latencies • Widely varying data transfer rates I/O Device I/O Device I/O Device

13. The General Organization of a Bus • Control lines: • Signal requests and acknowledgments • Indicate what type of information is on the data lines • Data lines carry information between the source and the destination: • Data and Addresses • Complex commands Control Lines Data Lines

14. Master versus Slave • A bus transaction includes two parts: • Issuing the command (and address) – request • Transferring the data – action • Master is the one who starts the bus transaction by: • issuing the command (and address) • Slave is the one who responds to the address by: • Sending data to the master if the master ask for data • Receiving data from the master if the master wants to send data Master issues command Bus Master Bus Slave Data can go either way

15. What is DMA (Direct Memory Access)? • Typical I/O devices must transfer large amounts of data to memory of processor: • Disk must transfer complete block (4K? 16K?) • Large packets from network • Regions of frame buffer • DMA gives external device ability to write memory directly: much lower overhead than having processor request one word at a time. • Processor (or at least memory system) acts like slave • Issue: Cache coherence: • What if I/O devices write data that is currently in processor Cache? • The processor may never see new data! • Solutions: • Flush cache on every I/O operation (expensive) • Have hardware invalidate cache lines (remember “Coherence” cache misses?)

16. Types of Buses • Processor-Memory Bus (design specific) • Short and high speed • Only need to match the memory system • Maximize memory-to-processor bandwidth • Connects directly to the processor • Optimized for cache block transfers • I/O Bus (industry standard) • Usually is lengthy and slower • Need to match a wide range of I/O devices • Connects to the processor-memory bus or backplane bus • Backplane Bus (standard or proprietary) • Backplane: an interconnection structure within the chassis • Allow processors, memory, and I/O devices to coexist • Cost advantage: one bus for all components

17. Example: Pentium System Organization Processor/Memory Bus PCI Bus I/O Busses

18. A Computer System with One Bus: Backplane Bus • A single bus (the backplane bus) is used for: • Processor to memory communication • Communication between I/O devices and memory • Advantages: Simple and low cost • Disadvantages: slow and the bus can become a major bottleneck • Example: IBM PC - AT Backplane Bus Processor Memory I/O Devices

19. Processor Memory Bus Processor Memory Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus I/O Bus A Two-Bus System • I/O buses tap into the processor-memory bus via bus adaptors: • Processor-memory bus: mainly for processor-memory traffic • I/O buses: provide expansion slots for I/O devices • Apple Macintosh-II • NuBus: Processor, memory, and a few selected I/O devices • SCCI Bus: the rest of the I/O devices

20. Processor Memory Bus Processor Memory Bus Adaptor Backside Cache bus Bus Adaptor I/O Bus L2 Cache I/O Bus Bus Adaptor A Three-Bus System (+ backside cache) • A small number of backplane buses tap into the processor-memory bus • Processor-memory bus is only used for processor-memory traffic • I/O buses are connected to the backplane bus • Advantage: loading on the processor bus is greatly reduced

21. Main componenets of Intel Chipset: Pentium II/III • Northbridge: • Handles memory • Graphics • Southbridge: I/O • PCI bus • Disk controllers • USB controlers • Audio • Serial I/O • Interrupt controller • Timers

22. What defines a bus? Transaction Protocol Timing and Signaling Specification Bunch of Wires Electrical Specification Physical / Mechanical Characteristics – the connectors

23. Synchronous and Asynchronous Bus • Synchronous Bus: • Includes a clock in the control lines • A fixed protocol for communication that is relative to the clock • Advantage: involves very little logic and can run very fast • Disadvantages: • Every device on the bus must run at the same clock rate • To avoid clock skew, they cannot be long if they are fast • Asynchronous Bus: • It is not clocked • It can accommodate a wide range of devices • It can be lengthened without worrying about clock skew • It requires a handshaking protocol

24. Busses so far Master Slave Bus Master: has ability to control the bus, initiates transaction Bus Slave: module activated by the transaction Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req, ack) serve to orchestrate sequencing. Synchronous Bus Transfers: sequence relative to common clock. ° ° ° Control Lines Address Lines Data Lines

25. Bus Transaction • Arbitration: Who gets the bus • Request: What do we want to do • Action: What happens in response

26. Arbitration: Obtaining Access to the Bus Control: Master initiates requests • One of the most important issues in bus design: • How is the bus reserved by a device that wishes to use it? • Chaos is avoided by a master-slave arrangement: • Only the bus master can control access to the bus: It initiates and controls all bus requests • A slave responds to read and write requests • The simplest system: • Processor is the only bus master • All bus requests must be controlled by the processor • Major drawback: the processor is involved in every transaction Bus Master Bus Slave Data can go either way

27. Multiple Potential Bus Masters: the Need for Arbitration • Bus arbitration scheme: • A bus master wanting to use the bus asserts the bus request • A bus master cannot use the bus until its request is granted • A bus master must signal to the arbiter after finish using the bus • Bus arbitration schemes usually try to balance two factors: • Bus priority: the highest priority device should be serviced first • Fairness: Even the lowest priority device should never be completely locked out from the bus • Bus arbitration schemes can be divided into four broad classes: • Daisy chain arbitration • Centralized, parallel arbitration • Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. • Distributed arbitration by collision detection: Each device just “goes for it”. Problems found after the fact.

28. The Daisy Chain Bus Arbitrations Scheme • Advantage: simple • Disadvantages: • Cannot assure fairness: A low-priority device may be locked out indefinitely • The use of the daisy chain grant signal also limits the bus speed Device 1 Highest Priority Device N Lowest Priority Device 2 Grant Grant Grant Release Bus Arbiter Request wired-OR

29. Centralized Parallel Arbitration • Used in essentially all processor-memory busses and in high-speed I/O busses Device 1 Device N Device 2 Req Grant Bus Arbiter

30. Simplest bus paradigm • All agents operate synchronously • All can source / sink data at same rate • => simple protocol • just manage the source and target

31. Simple Synchronous Protocol • Even memory busses are more complex than this • memory (slave) may take time to respond • it may need to control data rate BReq BG R/W Address Cmd+Addr Data1 Data2 Data

32. Typical Synchronous Protocol • Slave indicates when it is prepared for data xfer • Actual transfer goes at bus rate BReq BG R/W Address Cmd+Addr Wait Data1 Data1 Data2 Data

33. Increasing the Bus Bandwidth • Separate versus multiplexed address and data lines: • Address and data can be transmitted in one bus cycleif separate address and data lines are available • Cost: (a) more bus lines, (b) increased complexity • Data bus width: • By increasing the width of the data bus, transfers of multiple words require fewer bus cycles • Example: SPARCstation 20’s memory bus is 128 bit wide • Cost: more bus lines • Block transfers: • Allow the bus to transfer multiple words in back-to-back bus cycles • Only one address needs to be sent at the beginning • The bus is not released until the last word is transferred • Cost: (a) increased complexity (b) decreased response time for request

34. Increasing Transaction Rate on Multimaster Bus • Overlapped arbitration • perform arbitration for next transaction during current transaction • Bus parking • master can holds onto bus and performs multiple transactions as long as no other master makes request • Overlapped address / data phases (prev. slide) • requires one of the above techniques • Split-phase (or packet switched) bus • completely separate address and data phases • arbitrate separately for each • address phase yield a tag which is matched with data phase • ”All of the above” in most modern buses

35. 1993 MP Server Memory Bus Survey: GTL revolution Bus MBus Summit Challenge XDBus Originator Sun HP SGI Sun Clock Rate (MHz) 40 60 48 66 Address lines 36 48 40 muxed Data lines 64 128 256 144 (parity) Data Sizes (bits) 256 512 1024 512 Clocks/transfer 4 5 4? Peak (MB/s) 320(80) 960 1200 1056 Master Multi Multi Multi Multi Arbitration Central Central Central Central Slots 16 9 10 Busses/system 1 1 1 2 Length 13 inches 12? inches 17 inches

36. Asynchronous Handshake Write Transaction t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target. t1: Master asserts request line t2: Slave asserts ack, indicating data received t3: Master releases req t4: Slave releases ack Address Data Read Req Ack Master Asserts Address Next Address Master Asserts Data t0 t1 t2 t3 t4 t5

37. Read Transaction t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target. t1: Master asserts request line t2: Slave asserts ack, indicating ready to transmit data t3: Master releases req, data received t4: Slave releases ack Address Data Read Req Ack Master Asserts Address Next Address Slave Data t0 t1 t2 t3 t4 t5

38. 1993 Backplane/IO Bus Survey Bus SBus TurboChannel MicroChannel PCI Originator Sun DEC IBM Intel Clock Rate (MHz) 16-25 12.5-25 async 33 Addressing Virtual Physical Physical Physical Data Sizes (bits) 8,16,32 8,16,24,32 8,16,24,32,64 8,16,24,32,64 Master Multi Single Multi Multi Arbitration Central Central Central Central 32 bit read (MB/s) 33 25 20 33 Peak (MB/s) 89 84 75 111 (222) Max Power (W) 16 26 13 25

39. Some Example Problems • Let’s look at some examples from the text “Performance Analysis of Synchronous vs. Asynchronous” “Performance Analysis of Two Bus Schemes”

40. Other important issues • Bus Arbitration: — daisy chain arbitration (not very fair) — centralized arbitration (requires an arbiter), e.g., PCI — self selection, e.g., NuBus used in Macintosh — collision detection, e.g., Ethernet • Operating system: — polling — interrupts — DMA • Performance Analysis techniques: — queuing theory — simulation — analysis, i.e., find the weakest link (see “I/O System Design”) • Many new developments

41. Giving Commands to I/O Devices • Two methods are used to address the device: • Special I/O instructions • Memory-mapped I/O • Special I/O instructions specify: • Both the device number and the command word • Device number: the processor communicates this via aset of wires normally included as part of the I/O bus • Command word: this is usually send on the bus’s data lines • Memory-mapped I/O: • Portions of the address space are assigned to I/O device • Read and writes to those addresses are interpretedas commands to the I/O devices • User programs are prevented from issuing I/O operations directly: • The I/O address space is protected by the address translation

42. Memory Mapped I/O CPU Single Memory & I/O Bus No Separate I/O Instructions ROM RAM Memory Interface Interface Peripheral Peripheral CPU $ I/O L2 $ Memory Bus I/O bus Memory Bus Adaptor

43. I/O Device Notifying the OS • The OS needs to know when: • The I/O device has completed an operation • The I/O operation has encountered an error • This can be accomplished in two different ways • I/O Interrupt: • Whenever an I/O device needs attention from the processor,it interrupts the processor from what it is currently doing. • Polling: • The I/O device put information in a status register • The OS periodically check the status register

44. I/O Interrupt • An I/O interrupt is just like the exceptions except: • An I/O interrupt is asynchronous • Further information needs to be conveyed • An I/O interrupt is asynchronous with respect to instruction execution: • I/O interrupt is not associated with any instruction • I/O interrupt does not prevent any instruction from completion • You can pick your own convenient point to take an interrupt • I/O interrupt is more complicated than exception: • Needs to convey the identity of the device generating the interrupt • Interrupt requests can have different urgencies: • Interrupt request needs to be prioritized

45. Raise priority Reenable All Ints Save registers  lw $r1,20($r0) lw $r2,0($r1) addi $r3,$r0,#5 sw $r3,0($r1)  Restore registers Clear current Int Disable All Ints Restore priority RTI PC saved Disable All Ints Supervisor Mode  add $r1,$r2,$r3 subi $r4,$r1,#4 slli $r4,$r4,#2 Hiccup(!) lw $r2,0($r4) lw $r3,4($r4) add $r2,$r2,$r3 sw 8($r4),$r2  External Interrupt “Interrupt Handler” Restore PC User Mode Example: Device Interrupt • Advantage: • User program progress is only halted during actual transfer • Disadvantage, special hardware is needed to: • Cause an interrupt (I/O device) • Detect an interrupt (processor) • Save the proper states to resume after the interrupt (processor)

46. Disable Network Intr  subi $r4,$r1,#4 slli $r4,$r4,#2 lw $r2,0($r4) lw $r3,4($r4) add $r2,$r2,$r3 sw 8($r4),$r2 lw $r1,12($zero) beq $r1,no_mess lw $r1,20($r0) lw $r2,0($r1) addi $r3,$r0,#5 sw 0($r1),$r3 Clear Network Intr  External Interrupt Polling Point (check device register) “Handler” no_mess: Alternative: Polling

47. CPU Memory IOC device Polling: Programmed I/O • Advantage: • Simple: the processor is totally in control and does all the work • Disadvantage: • Polling overhead can consume a lot of CPU time Is the data ready? busy wait loop not an efficient way to use the CPU unless the device is very fast! no yes read data but checks for I/O completion can be dispersed among computation intensive code store data no done? yes

48. Polling is faster/slower than Interrupts • Polling is faster than interrupts because • Compiler knows which registers in use at polling point. Hence, do not need to save and restore registers (or not as many). • Other interrupt overhead avoided (pipeline flush, trap priorities, etc). • Polling is slower than interrupts because • Overhead of polling instructions is incurred regardless of whether or not handler is run. This could add to inner-loop delay. • Device may have to wait for service for a long time. • When to use one or the other? • Multi-axis tradeoff • Frequent/regular events good for polling, as long as device can be controlled at user level. • Interrupts good for infrequent/irregular events • Interrupts good for ensuring regular/predictable service of events.

49. Delegating I/O Responsibility from the CPU: DMA CPU sends a starting address, direction, and length count to DMAC. Then issues "start". • Direct Memory Access (DMA): • External to the CPU • Act as a maser on the bus • Transfer blocks of data to or from memory without CPU intervention CPU Memory DMAC IOC device DMAC provides handshake signals for Peripheral Controller, and Memory Addresses and handshake signals for Memory.

50. Delegating I/O Responsibility from the CPU: IOP D1 IOP CPU D2 main memory bus Mem . . . Dn I/O bus target device where cmnds are OP Device Address CPU IOP (1) Issues instruction to IOP (4) IOP interrupts CPU when done IOP looks in memory for commands (2) OP Addr Cnt Other (3) memory what to do special requests Device to/from memory transfers are controlled by the IOP directly. IOP steals memory cycles. where to put data how much