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TMB Mezzanine SEU Testing Preliminary Results

TMB Mezzanine SEU Testing Preliminary Results. TAMU Cyclotron Beam Test July 2011. J. Gilmore for the TAMU CMS Group. Cyclotron Operation. H 2 + molecule beam, 55 MeV per proton Maximum flux ~1.5 *10 7 cm -2 s -1 Beam collimated to 1.5” diam beam spot

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TMB Mezzanine SEU Testing Preliminary Results

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  1. TMB Mezzanine SEU TestingPreliminary Results TAMU Cyclotron Beam Test July 2011 J. Gilmore for the TAMU CMS Group

  2. Cyclotron Operation • H2+ molecule beam, 55 MeV per proton • Maximum flux ~1.5 *107 cm-2s-1 • Beam collimated to 1.5” diam beam spot • 45 to 90 minute runs on each target device • Typical dose in the 5 to 10 kRad range

  3. Expected SLHC Environment • Assume 5x LHC rates using ME1/1 as baseline • Use SLHC peak Luminosity = 5*1034 cm-2s-1 • For SEU look at neutron fluence > 20 MeV • Huhtinen estimates 5.4 *109 cm-2 per year average • Defines a year as 180 running days • Converts to 1.5 *108 n/cm2 per day at SLHC • Makes some assumptions • Average luminosity during a fill (half peak)  safe? • Averages neutron rate over the ME1/1 region • No uncertainty factor is included • We should include factor *3 to be conservative  Maybe *5 is better?

  4. Snap12 Tx Results • Board 1: PRBG data sent over six links @ 3.2 Gb/s • 6 SEUs observed with 7.04*1010 p/cm2 fluence • s = 8.52 *10-11 cm2 • Board 2: PRBG data sent over six links @ 3.2 Gb/s • 3 SEUs observed with 5.28*1010 p/cm2 fluence • s = 5.68 *10-11 cm2 • Combined results for both boards • s = (7.31 ± 2.44) *10-11 cm2 • ~0.011 SEU/day per chip at SLHC

  5. Snap12 Rx Results • Board 1: six links operational • 278 SEUs observed with 3.26*1010 p/cm2 fluence • s = (8.53 ± .51) *10-9 cm2 • Board 2: six links operational • 311 SEUs observed with 3.94*1010 p/cm2 fluence • s = (7.90 ± .45) *10-9 cm2 • Two of these SEUs required FPGA reset to recover • Lost link lock? • Combined results for both boards • s = (8.18 ± .34) *10-9 cm2 • ~1.2 SEU/day per chip at SLHC

  6. TI Level Shifting Translator Results • Board 1: 24-bit PRBG data sent @ 15 MHz • 0 SEUs observed with 5.68*1010 p/cm2 fluence • s90% < 4.05 *10-11 cm2 • Board 2: 24-bit PRBG data sent @ 15 MHz • 0 SEUs observed with 7.62*1010 p/cm2 fluence • s90% < 3.02 *10-11 cm2 • Combined results for both boards • s90% < 1.73 *10-11 cm2 • < 0.0026 SEU/day per chip at SLHC

  7. Finisar Optical Transceiver Results • Board 1: 8 kB GbE packets sent @ 75/sec • 6 SEUs observed with 7.62*1010 p/cm2 fluence • s = 7.87 *10-11 cm2 • 3 SEUs persistent, required power cycle to recover • Board 2: 8 kB GbE packets sent @ 75/sec • 8 SEUs observed with 6.04*1010 p/cm2 fluence • s = 1.32 *10-10 cm2 • 5 SEUs persistent, required power cycle to recover • Combined results for both boards • s = (1.02 ± .27) *10-10 cm2 • ~0.015 SEU/day per chip at SLHC

  8. FPGA SEU Tests • SEU tests performed during FPGA exposure • Verification of ROM contents in BRAMs • Verification of ROM contents in CLBs • Finisar and Snap12 operations test GTX sensitivity • Translator operations test CLB and I/O sensitivity • Test firmware utilized a lot of FPGA resources: • 256 BRAMs (74%) • 7 serial transceiver pairs in 11 GTX blocks (55%) • 11,919 Slices (38%) • There is no mitigation logic in this firmware • The SEU rates determined here can be improved upon

  9. FPGA BRAM Results • Board 1: ROM contents checked at PC • 61 SEUs observed with 10.5*108 p/cm2 fluence • 5 of these were multi-byte errors • s = 5.81 *10-8 cm2 • Board 2 : ROM contents checked at PC • 34 SEUs observed with 6.20*108 p/cm2 fluence • None of these were multi-byte errors • s = 5.48 *10-8 cm2 • Combined results for both boards • s = (5.69 ± .58) *10-8 cm2 • ~8.5 SEU/day per chip at SLHC

  10. FPGA CLB Results • Board 1: ROM contents checked at PC • 40 SEUs observed with 10.5*108 p/cm2 fluence • 20 of these were multi-byte errors • s = 3.81 *10-8 cm2 • Board 2 : ROM contents checked at PC • 22 SEUs observed with 6.20*108 p/cm2 fluence • 7 of these were multi-byte errors • s = 3.55 *10-8 cm2 • Combined results for both boards • s = (3.71 ± .47) *10-8 cm2 • ~5.6 SEU/day per chip at SLHC

  11. FPGA GTX Results • Board 1: PRBG data and GbE packet checks • 48 Snap12 SEUs observed, 41 required reset • 4 GbE SEUs, all 4 required reset • 52SEUs, 6.52*1010 p/cm2 fluence: s = 7.98 *10-10 cm2 • Board 2 : PRBG data and GbE packet checks • 33 Snap12 SEUs observed, 30 required reset • 6 GbE SEUs, all 6 required reset • 39SEUs, 5.54*1010 p/cm2 fluence: s = 7.04 *10-10 cm2 • Combined results for both boards • s = (7.55 ± .79) *10-10 cm2 • ~0.11 SEU/day per chip at SLHC

  12. Estimate of ME1/1 SEU Rates • Virtex 6 FPGAs • Assume 1 each on TMB, DMB and DCFEB: 648 total • These may have 15 SEU/day: ~7 SEU/min for all ME1/1 • Snap12 Rx • Assume 1 each on TMB and DMB: 144 total • These may have 1.2 SEU/day: ~.1 SEU/min for all ME1/1 • Snap12 Tx • Assume 1 on DMB: 72 total • These may have .01 SEU/day: ~.0005 SEU/min for all ME1/1 • Finisar optical transceiver • Assume 3 on DCFEB: 1512 total • These may have .015 SEU/day: ~.016 SEU/min for all ME1/1

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