FZI Forschungszentrum Informatik at the University of Karlsruhe

1. FZI Forschungszentrum Informatikat the University of Karlsruhe Power Estimation Approach for SRAM-based FPGAs FZI Embedded System Design Group (ESDG) Karlheinz Weiss, Thorsten Steckstor, Wolfgang Rosenstiel Forschungszentrum Informatik, Karlsruhe

2. Overview • Introduction • State of the art • Estimating Power Consumption for Virtex • technology power factor Kp(Virtex) • benchmark test design • SPYDER-System • SPYDER-VIRTEX-X2 • SPYDER-CORE-P2/SH3 (7709A/7729-DSP) • Experimental Results • Current work in progress • SPYDER-VIRTEX-X2E

3. Introduction • FPGA development in the last few years • significant increase in on-chip gate capacity • decrease in run-times through programmable logic • Dramatically increase of the power consumption • circuit speed (in terms of average clock frequency) • utilized chip area (in terms of CLBs, routing length and IOs) • Problems for embedded system design • FPGAs can consume several amperes of current • appropriate board design for power supply is needed • sufficient ambient conditions to carry of the heat must be provided • Solution: • Estimation of power consumption in an early design step

4. State of the Art: XC4000 architecture • PEST = PSTAT + PIO + PINT • PSTAT : static power (few microwatts) • PIO = PDC + PAC : IO-power • PINT : internal power (important) >> Kp(Virtex) ??

5. Estimating Power for Virtex PINT : measured on SPYDER-VIRTEX-X2 VCore := 2.5 V fMax: constrain from the development tool NLC := 2.25 x nSlice (output development tool) TogLC : can be set to 1

6. SPYDER-System second generation

7. Configuration- Flash 2M x 8 Memory Add-On Board 4M x 32 SDRAM or 256k x 32 SSRAM or 1M x 32 Flash C-API-Routines for NT 4.0 86 I Memory Add-On Board 4M x 32 SDRAM or 256k x 32 SSRAM or 1M x 32 Flash II connection to CORE-tools SSRAM 256k x 32 or SDRAM 4M x 32 SSRAM 256k x 32 or SDRAM 4M x 32 SPYDER-VIRTEX-X2: architecture arbiter external FPGA configuration header (parallel port) CPLD XC95144xl configuration Xilinx-Virtex-FPGA I PCI-interface microcontroller XCV300...XCV800 PCI - SLOT 30 PLX-PCI9080 86 32 II BGA 432 extension header I and II power supply + 2,5V or 1,8V / 10A + 3,3V / 3A high density logic analyzer connectors

8. Experimental Results small middle large

9. Experimental Results Worst Case Scenarios

10. scaleable in size Xilinx Virtex FPGA (provide up to 2 mio. gates) XCV1000E up to XCV2000E BGA 560 Xilinx Virtex FPGA (provide up to 2 mio. gates) XCV1000E up to XCV2000E BGA 560 86 86 IV IV not visible to the user Configuration SH3-7709A core 8MB Flash 100/10BaseT ethernet 86 86 III III back planes 86 86 II II VxWorks inside 86 86 I I LAN/WAN Intra/Internet (TCP/IP) Third generation SSRAM 256k x 32 or SDRAM 4M x 32 SSRAM 256k x 32 or SDRAM 4M x 32 SSRAM 256k x 32 or SDRAM 4M x 32 SSRAM 256k x 32 or SDRAM 4M x 32 power supply + 2,5V or 1,8V / 10A + 3,3V / 3A Current work: SPYDER-VIRTEX-X3E high density logic analyzer connectors extension headers I to IV

11. Conclusion • Estimating power consumption in an early design step • used the kown approach for XC4000 • extended that approach to the novel Virtex architecture • Work was done using the SPYDER-tool set • especially SPYDER-VIRTEX-X2 • PCI-based Virtex-FPGA emulation platform • Experimental Result • Kp(Virtex) = 4.6 x 10-12 • about 2.5 better than XC4000XV-family • Current work: SPYDER-VIRTEX-X3E • Intra/Internet accessible

12. Picture of SPYDER-VIRTEX-X2 Further information: http://www.fzi.de/sim/spyder.html - user manual - application notes - support software download - IP-cores - all accepted papers of the ESDG You are invited to see a demonstration outside now!