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VLSI Design Lecture 4-b: Layout Extraction

VLSI Design Lecture 4-b: Layout Extraction. Mohammad Arjomand CE Department Sharif Univ. of Tech. Gate Layout. Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Must follow a technology rule Standard cell design methodology

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VLSI Design Lecture 4-b: Layout Extraction

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  1. VLSI DesignLecture 4-b: Layout Extraction Mohammad Arjomand CE Department Sharif Univ. of Tech.

  2. Gate Layout • Layout can be very time consuming • Design gates to fit together nicely • Build a library of standard cells • Must follow a technology rule • Standard cell design methodology • VDD and GND should abut (standard height) • Adjacent gates should satisfy design rules • nMOS at bottom and pMOS at top • All gates include well and substrate contacts

  3. Example: Inverter

  4. Layout using Electric

  5. Example: NAND3 • Horizontal N-diffusion and p-diffusion strips • Vertical polysilicon gates • Metal1 VDD rail at top • Metal1 GND rail at bottom • 32  by 40 

  6. Example: NAND3

  7. Stick Diagrams • Stick diagrams help plan layout quickly • Need not be to scale • Draw with color pencils or dry-erase markers

  8. VDD Vin Vout GND Stick Diagrams • Stick diagrams help plan layout quickly • Need not be to scale • Draw with color pencils or dry-erase markers

  9. Wiring Tracks • A wiring track is the space required for a wire • 4  width, 4  spacing from neighbor = 8  pitch • Transistors also consume one wiring track

  10. Well spacing • Wells must surround transistors by 6  • Implies 12  between opposite transistor flavors • Leaves room for one wire track

  11. Area Estimation • Estimate area by counting wiring tracks • Multiply by 8 to express in 

  12. Example: O3AI • Sketch a stick diagram for O3AI and estimate area

  13. Example: O3AI • Sketch a stick diagram for O3AI and estimate area

  14. Example: O3AI • Sketch a stick diagram for O3AI and estimate area

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